Abstract: A video decoding device for a TV receiver, e.g., SDTV, decodes a compressed video signal transmitted from a transmitting side and displays the decoded signal. The device includes a first downsampling part for downsampling input data in a unit of block at a predetermined ratio; a display size converting part for dividing the downsampled result into a first group of data and a second group of data and after downsampling the first group of data, for performing screen format conversion for the downsampled first group of data into a display size; a memory for storing each of the converted first group of data and the second group of data; and an output part for downsampling the second group of data to correspond with the first group of data to thereby perform screen format conversion for the downsampled second group of data, when the second group of data is reproduced, and for outputting the first and second groups of data.

Abstract: A memory structure and method for implementing an on screen display (OSD) is disclosed. The present invention separates a command area, which stores small but frequently updated data causing fatal errors due to erroneous read, from a bitmap area, which stores relatively larger data, less frequently updated than the command area and which is not sensitive to errors. Thus, OSD memory structure and method allows an external host processor to effectively control the OSD process. Also, the command area further comprises a global command and a plurality of local commands, wherein the global command contains common control information to the local commands and control information other than OSD information, thereby allowing the external host processor to effectively control the OSD even when implementing multistandard OSD where a plurality of bitmap and commands for these bitmap are constructed in an external memory.

Abstract: An apparatus for a fast inverse discrete cosine transform (IDCT) by processing only non-zero IDCT input data including non-zero feeding unit connected to each row-column decomposed one dimensional IDCT input for feeding only non-zero input data during each cycle. The first 1-D IDCT and the second 1-D IDCT have the same structure, and 1-D IDCT core with a non-zero feeding unit at its front end. The 1-D IDCT core of the present invention is for performing IDCT operation based on the input scaling method, and the operation of the IDCT core consists of a cosine kernel selection operation using a received non-zero input, multiplication-and-addition, and a storing operation. The non-zero feeding unit for the first 1-D IDCT and the second one are different in their configuration. There are two different methods for implementing the first 1-D IDCT, a stored input feeding method and a zigzag scanned input feeding method.

Abstract: A decoder for a digital TV receiver is disclosed. The present decoder improves the picture quality of a video signal down converted when an SD class TV receiver receives an HD class video signal. Generally, the decoder receives data in block units, converts a format of the data into a format for display, memorizes the data, processes the memorized data, and displays the processed data by converting the format to include more horizontal color signals than vertical color signals, memorizing and reproducing the data in downsampling the data in block units in a given ratio, and storing the data.

Abstract: An inverse discrete cosine transforming (IDCT) system for a digital television receiver performing a variable length decoding and an inverse quantization of an applied bit stream and an IDCT with respect to inversely quantized DCT coefficients, including an integrated IDCT part which performs an inverse discrete cosine transformation of standards DCT coefficients inversely quantized or high definition DCT coefficients inversely quantized.

Abstract: A method for decoding MPEG standard I (Intra-coded) and P (Predictive-coded) picture bit streams using a memory smaller than one video frame of data.

Abstract: Improved variable code length decoder is disclosed, including a storage part for temporary storage and production of an encoded code word in response to a read signal, a switching part for selective production of the code words from the storage part in response to a switching signal, a barrel shifter for shifting a decoding output window thereon in response to a shift signal in producing a predetermined number of bits of the code word from the switching part for decoding, a storage part for temporary storage and production of the code word from the barrel shifter, a table for producing a decoded code word and a bit length of the code word of the predetermined number of bits stored in the storage part, and a control signal generating part for using the bit length of a code word at the present clock received from the table in generating the switching signal, the shift signal and the read signal.

Abstract: A high speed variable length code (VLC) decoder for decoding in real time data encoded in a system such as MPEG 1, MPEG 2 or HDTV (high definition television) includes a bit stream buffer, a data buffer, a pair of latch units, a pair of selectors, a barrel shifter, a VLC table random logic, an output buffer, an accumulator, and a VLC decoder controller. The VLC decoder controller appropriately controls data flow in the VLC decoder, by using a bit empty signal from the bit stream signal, a data empty signal from the data buffer, a data full signal from the output buffer and a carry signal from the accumulator.

Abstract: A bit pattern detector for detecting a bit pattern in a parallel bitstream input includes left and right matching units for detecting bits in the bitstream input that match the bit pattern. The left matching unit outputs a plurality of signals to an adder, a multiplexer, and a pattern detector, depending on whether and how many matching bits are detected in the bitstream input. The right matching unit also outputs a signal to the adder. The pattern detector outputs a detection signal depending on the input from the left matching unit and the adder, and also outputs a control signal to the multiplexer. The multiplexer selects and outputs a signal from amongst the signals received thereby from the left matching unit and a size signal corresponding to a size of the bitstream input. The detector also may include a bit pattern register which stores the bit pattern and provides it to the left and right matching units, and a bit number register for storing the signal received from the right matching unit.