Patents by Inventor Seong-soo Lee

Seong-soo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6743695
    Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: June 1, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Soo Lee, Jae-Seung Hwang
  • Publication number: 20040027300
    Abstract: An isotropic antenna system includes a first antenna for transmitting/receiving electric waves when a cover member installed to be capable of being open or closed with respect to a main body is open, a second antenna for transmitting/receiving electric waves when the cover member is closed, and a switching portion for selectively switching at least one of the first and second antennas to a predetermined RF circuit module according to the opening or closing of the cover member.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 12, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Eil Kim, Jae-Yul Lee, Seong-Soo Lee
  • Publication number: 20040014435
    Abstract: A multi-band radio frequency (RF) receiving method in a mobile communication system having a reduced size and cost includes receiving RF wave signals for four or more non-overlapping bands, primarily filtering a first wide band including adjacent first and second bands and a second wide band including adjacent third and fourth bands from the received RF wave signals, low-noise amplifying the RF wave signals of the first and second wide bands, respectively, secondarily filtering a third wide band including adjacent second and third bands and a fourth wide band including first and fourth bands from the low-noise amplified RF wave signals of the first and second wide bands, generating two band RF wave signals to be simultaneously received, and frequency-down converting the two band RF wave signals generated in the secondary filtering step into two band intermediate frequency wave signals by means of first and second oscillation frequencies.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 22, 2004
    Inventors: Sang-Hyun Woo, Seong-Soo Lee, Jong-Ae Park
  • Publication number: 20030199149
    Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.
    Type: Application
    Filed: January 29, 2003
    Publication date: October 23, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-Soo Lee, Jae-Seung Hwang
  • Patent number: 6628236
    Abstract: An isotropic antenna system includes a first antenna for transmitting/receiving electric waves when a cover member installed to be capable of being open or closed with respect to a main body is open, a second antenna for transmitting/receiving electric waves when the cover member is closed, and a switch for selectively switching at least one of the first and second antennas to a predetermined RF circuit module according to the opening or closing of the cover member.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 30, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-eil Kim, Jae-yul Lee, Seong-soo Lee
  • Patent number: 6614328
    Abstract: Disclosed is a radio frequency filter of a combline structure including a frequency cut-off circuit for cutting off a specific frequency from a frequency band having a given frequency bandwidth. The frequency cut-off circuit includes an inductive transmission line extending from the output terminal by a length determined to provide an approximate inductance corresponding to a calculated value approximate to an inductance for obtaining the specific frequency, and a capacitive element coupled to the approximate inductance provided by the inductive transmission line, so that it has a capacitance for obtaining the specific frequency. The inductive transmission line is connected to the capacitive element through a via hole formed at an end of the transmission line opposite to the output terminal, from which the transmission line extends. The invention also proposes a method for implementing the radio frequency filter.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: September 2, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Hyun Son, Seong-Soo Lee
  • Patent number: 6583008
    Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 24, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-soo Lee, Jae-seung Hwang
  • Patent number: 6573139
    Abstract: A method of forming a floating gate electrode of a cell of a flash memory device having an interval less than a critical dimension (CD) in a conventional photolithographic process, in which the reliability of a dielectric layer does not deteriorate and damage to a floating gate electrode during etching is prevented, is provided. According to the present invention, a protective layer formed of a material having a high etching selectivity with respect to a device isolation layer and a doped polysilicon layer is formed on the upper surface of the doped polysilicon layer forming the floating gate electrode. The protective layer is partially etched and includes a recess. Next, a material layer for forming a spacer, which is formed of a material having a high etching selectivity with respect to the device isolation layer and the doped polysilicon layer, is formed on the upper surface of the protective layer and is etched back, thus forming the spacer.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: June 3, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-soo Lee, Joon Kim, Kang-ill Seo
  • Publication number: 20030022446
    Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 30, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-Soo Lee, Jae-Seung Hwang
  • Publication number: 20020171514
    Abstract: Disclosed is a radio frequency filter of a combline structure including a frequency cut-off circuit for cutting off a specific frequency from a frequency band having a given frequency bandwidth. The frequency cut-off circuit includes an inductive transmission line extending from the output terminal by a length determined to provide an approximate inductance corresponding to a calculated value approximate to an inductance for obtaining the specific frequency, and a capacitive element coupled to the approximate inductance provided by the inductive transmission line, so that it has a capacitance for obtaining the specific frequency. The inductive transmission line is connected to the capacitive element through a via hole formed at an end of the transmission line opposite to the output terminal, from which the transmission line extends. The invention also proposes a method for implementing the radio frequency filter.
    Type: Application
    Filed: February 25, 2002
    Publication date: November 21, 2002
    Applicant: SAMSUNG ELECTRONICS Co., Ltd.
    Inventors: Mi-Hyun Son, Seong-Soo Lee
  • Patent number: 6483146
    Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: November 19, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-soo Lee, Jae-seung Hwang
  • Publication number: 20020052082
    Abstract: A method of forming a floating gate electrode of a cell of a flash memory device having an interval less than a critical dimension (CD) in a conventional photolithographic process, in which the reliability of a dielectric layer does not deteriorate and damage to a floating gate electrode during etching is prevented, is provided. According to the present invention, a protective layer formed of a material having a high etching selectivity with respect to a device isolation layer and a doped polysilicon layer is formed on the upper surface of the doped polysilicon layer forming the floating gate electrode. The protective layer is partially etched and includes a recess. Next, a material layer for forming a spacer, which is formed of a material having a high etching selectivity with respect to the device isolation layer and the doped polysilicon layer, is formed on the upper surface of the protective layer and is etched back, thus forming the spacer.
    Type: Application
    Filed: July 12, 2001
    Publication date: May 2, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-Soo Lee, Joon Kim, Kang-Ill Seo
  • Publication number: 20010052878
    Abstract: An isotropic antenna system includes a first antenna for transmitting/receiving electric waves when a cover member installed to be capable of being open or closed with respect to a main body is open, a second antenna for transmitting/receiving electric waves when the cover member is closed, and a switch for selectively switching at least one of the first and second antennas to a predetermined RF circuit module according to the opening or closing of the cover member.
    Type: Application
    Filed: March 1, 2001
    Publication date: December 20, 2001
    Inventors: Young-eil Kim, Jae-yul Lee, Seong-soo Lee
  • Publication number: 20010015454
    Abstract: A floating gate electrode configuration and process reduces a space critical dimension between adjacent floating gate electrodes while reducing the consumption of a device isolation layer during etching of a dielectric layer overlying the floating gate electrode. The end portions of the floating gate electrode, which is formed separated on a device isolation region, have a step or rounded pattern. In order to realize such a pattern, after a first partial etch of a floating gate electrode material, polymer spacers or silicon nitride spacers are formed along the etched sidewalls. Then, using those spacers as an etching mask, a second etch is performed on the floating gate electrode material to separate the same. Furthermore, after forming polysilicon on the partially etched floating gate electrode material, blanket etching is performed on the polysilicon to form a floating gate electrode having a round pattern of end portions.
    Type: Application
    Filed: December 13, 2000
    Publication date: August 23, 2001
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Seong-soo Lee, Jae-seung Hwang