Abstract: The present invention relates to identification of the consensus sequence phosphorylated by ATM kinase. This, in turn, permitted identification of ATM kinase target proteins, and development of a convenient assay system for ATM kinase phosphorylation using fusion polypeptides as substrates. The assay system is adaptable to screening for ATM modulators, particularly inhibitors. In a specific embodiment, the substrate recognition sequence and mutagenized variants of this sequence were incorporated in a GST fusion protein and assayed for phosphorylation by ATM kinase. This assay system is useful in screening for ATM inhibitors. ATM function assays were validated using an ATM-kinase dead dominant-negative mutant.

Abstract: A function display system of a camera including a switch block, an automatic distance measuring circuit, a brightness measuring circuit, a motor driving circuit, and a function display unit. The CPU causes the function display unit to display each camera function in serial order after a power switch is pressed, thereby informing the user of camera functions. When a user presses a flash function or photograph function switch for a predetermined interval, the CPU changes camera sub-functions. The CPU displays a sub-function arranged by a user and a special sub-function arranged by a camera for a longer interval, allowing the user to select the sub-functions more easily. As a result, the camera display system and method provides a camera having improved convenience and efficiency.

Abstract: A camera capable of controlling the supply of power to the internal circuitry of the camera which includes a power supply for supplying power to the internal circuitry of the camera, circuitry for determining one or more photographic conditions associated with an object, and circuitry for concurrently activating the power supply and the determining circuitry to initiate a photograph taking operation.

Abstract: A known photoelectric sensor is utilized for optically detecting the presence of a tape cassette in a loading commencement position to produce an electrical driving signal. Responsive to the driving signal, an electric loading motor is activated to cause a loading arm to swing from one angular position to another angular position. Rotary movement of the loading motor is translated into a pivotal swinging movement of the loading arm by a unitary linkage lever. The linkage lever carries a light beam interrupter piece which may cut off the light beam projected by the photoelectric sensor to enable the latter to generate the electrical driving signal. The linkage lever also carries an arm locking finger adapted to lock the loading arm in a loading completion position. A reversible speed reduction gadget is employed in operatively coupling the linkage lever to the loading motor.

Abstract: A method for manufacturing a semiconductor device including a combined stack-trench type capacitor is disclosed. The method comprises the steps of: forming a conductive layer serving as a first electrode of the capacitor both on the inside region of a trench and on a transistor and forming a planarizing layer on the conductive layer; forming a photoresist pattern on the planarizing layer; etching the planarizing layer and the conductive layer; and removing the planarizing layer. The sandwiched planarizing layer between the second conductive layer and the photoresist pattern prevents the exposing of the first electrode pattern during the photoetching, so that uncontaminated uniform dielectric film can be obtained.

Abstract: A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.

Abstract: A highly integrated semiconductor memory device comprises a plurality of memory cells formed by alternately disposing a stack-type capacitor cell and a combined stack-trench type capacitor cell both in row and column directions. Each storage electrode of the capacitor of the memory cell is extended to overlap with the storage electrode of the capacitor of the adjacent memory cell. The combined stack-trench type capacitor is formed into the substrate to increase the storage capacitance thereof which allow the storage capacitance of the stack-type capacitor to increase by extending the storage electrode of the capacitor. Due to the alternate arrangement of stack-trench type capacitor and stack-type capacitor, step coverage, leakage current and soft errors of stack-trench type capacitor are prevented.

Abstract: A highly integrated semiconductor memory device comprises a plurality of memory cells formed by alternately disposing a stack-type capacitor cell and a combined stack-trench type capacitor cell both in row and column directions. Each storage electrode of the capacitor of the memory cell is extended to overlap with the storage electrode of the capacitor of the adjacent memory cell. The combined stack-trench type capacitor is formed into the substrate to increase the storage capacitance thereof which allow the storage capacitance of the stack-type capacitor to increase by extending the storage electrode of the capacitor. Due to the alternate arrangement of stack-trench type capacitor and stack-type capacitor, step coverage, leakage current and soft errors of stack-trench type capacitor are prevented.

Abstract: The method comprises the steps of: forming the transistor on a substrate and then depositing an interlayer insulating layer, and forming a design pattern of a first conductive layer by vertically etching it using a mask; horizontally overetching the pattern by using the etching process used for forming the pattern; depositing a first insulating film and then depositing the second conductive layer to the thickness needed to protect the first insulating film; vertically etching the second conductive layer, first insulating film and interlayer insulating layer by applying the mask used in vertically etching the first conductive layer; additionally depositing the second conductive layer; forming a design pattern of the second conductive layer by vertically etching it using a mask; horizontally overetching the pattern of the second conductive layer; depositing the second insulating film and then depositing a third conductive layer to have the thickness to protect the second insulating film; vertically etching the

Abstract: A method for manufacturing a combined stack-trench type capacitor includes forming a trench in the semiconductor substrate. A conductive layer, used as a first electrode, a dielectric film and another conductive layer, used as a second electrode, are deposited successively and continuously in the trench. The two conductive layers and the sandwiched dielectric film are then etched to form a capacitor pattern. An insulating layer is formed along the edges of the capacitor pattern, and then a third conductive layer is formed over the entire structure.

Abstract: A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer; a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer. The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.