Patents by Inventor Seong-Woo BAE

Seong-Woo BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072113
    Abstract: A vertical semiconductor device and method for manufacturing the same is provided. The semiconductor device includes a body with a substrate and an epitaxial layer on the substrate, the layer includes a first region of a first conductivity type, and a second region of a second different conductivity type, the second region is arranged opposite to the substrate with respect to the first region, and when viewed in a first direction from the layer to the substrate, the first region and the second region each extend across an entire area of the body. The device further includes a trench arranged in the body, extending through the second region and at least partially into the first region, thereby dividing the second region into an inner and an outer portion that are mutually electrically isolated, and a first conductive contact on the second region to enable electrically accessing the inner portion.
    Type: Application
    Filed: August 30, 2023
    Publication date: February 29, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Stefan Berglund, Tim Böttcher, Steffen Holland, Seong-Woo Bae, Detlef Oelgeschlaeger
  • Publication number: 20230307494
    Abstract: A vertical oriented semiconductor device is provided that includes a semiconductor body having a first major surface, the semiconductor body includes a first region of a first conductivity type, a second region of a second conductivity type, and the second region is adjacent the first region so that a junction is provided between the first region and the second region. The junction has a maximum distance to the first major surface, and the semiconductor device further includes a trench extending into the semiconductor body from the first major surface to an extension depth at least equal to the maximum distance. The trench includes a material arranged to provide electrical insulation to limit a lateral field termination distance associated with the junction.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 28, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Stefan Berglund, Steffen Holland, Tim Böttcher, Seong-Woo Bae
  • Patent number: 11206856
    Abstract: This invention relates to a sweetener containing an enzymatically modified stevia composition having improved sweetness quality, including 90 wt % or more of steviol glycoside, wherein only glycosylation is carried out using cyclodextrin as a glycosylation material of a stevia extract (steviol glycoside), without a purification process using an existing porous adsorbent resin (aromatic, styrene type), to thus produce enzymatically modified stevia, which can be utilized as an ingredient and a reagent for sweeteners, flavor enhancers and flavor modifiers for a variety of confections, drinks (including alcoholic beverages), foods and food products, thereby providing an enzymatically modified stevia sweetener and products thereof.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 28, 2021
    Assignee: DAEPYUNG CO., LTD.
    Inventors: Kyung-Jae Kim, Seong-Woo Bae, Rae-Kyoung Kim, Dong-Hwan Kim
  • Patent number: 10972074
    Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: April 6, 2021
    Assignee: Nexperia B.V.
    Inventors: Stefan Berglund, Soenke Habenicht, Michael Felix Konejung, Joachim Stange, Seong-Woo Bae
  • Patent number: 10720498
    Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Nexperia B.V.
    Inventors: Martin Roever, Soenke Habenicht, Stefan Berglund, Seong-Woo Bae
  • Publication number: 20190281873
    Abstract: This invention relates to a sweetener containing an enzymatically modified stevia composition having improved sweetness quality, including 90 wt % or more of steviol glycoside, wherein only glycosylation is carried out using cyclodextrin as a glycosylation material of a stevia extract (steviol glycoside), without a purification process using an existing porous adsorbent resin (aromatic, styrene type), to thus produce enzymatically modified stevia, which can be utilized as an ingredient and a reagent for sweeteners, flavor enhancers and flavor modifiers for a variety of confections, drinks (including alcoholic beverages), foods and food products, thereby providing an enzymatically modified stevia sweetener and products thereof.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 19, 2019
    Inventors: Kyung-Jae KIM, Seong-Woo BAE, Rae-Kyoung KIM, Dong-Hwan KIM
  • Publication number: 20190165111
    Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Applicant: NEXPERIA B.V.
    Inventors: Martin ROEVER, Soenke HABENICHT, Stefan BERGLUND, Seong-Woo BAE
  • Publication number: 20170302255
    Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 19, 2017
    Inventors: Stefan BERGLUND, Soenke HABENICHT, Michael Felix KONEJUNG, Joachim STANGE, Seong-Woo BAE