Patents by Inventor Seong-woon Booh
Seong-woon Booh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230176366Abstract: A system and method designing a metalens including nanostructures and a spacer layer between the nanostructures. The method includes; selecting a design area in relation to a width of the nanostructure and a pitch of the nanostructure, setting a search route in the design area in a direction in which a phase decreases, calculating transmittance at a reference point on the search route and change points near the reference point along the search route, determining the width of the nanostructure and the pitch of the nanostructure, generating a phase map corresponding to the width of the nanostructure and the pitch of the nanostructure, extracting an extracted width of the nanostructure and an extracted pitch of the nanostructure having a target phase from the phase map, and placing the nanostructure having the extracted width and extracted pitch in relation to the metalens corresponding to the target phase.Type: ApplicationFiled: November 25, 2022Publication date: June 8, 2023Inventors: HO YOUNG AHN, HYEON SOO PARK, SEONG WOON BOOH, KYU IL LEE, MUN BO SHIM, SEUNG HOON HAN
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Patent number: 10193250Abstract: According to example embodiments, a substrate for a power module includes a first part, a second part, and a third part on a same surface of an underlying part of the substrate. The first part, the second part, and the third part may be spaced apart from each other, electrically insulated from each other, and not directly contacting each other. The third part may surround the first part and the second part. A first element module may be on the third part. The first part, the second part, and the third part may be conductive.Type: GrantFiled: August 2, 2017Date of Patent: January 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Che-heung Kim, Chang-sik Kim, Seong-woon Booh
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Patent number: 9966782Abstract: A battery assembly including: at least one rechargeable lithium battery including a negative electrode including a silicon-containing negative active material selected from silicon, a silicon-carbon composite, and a combination thereof, and a positive electrode including a positive active material; a circuit board electrically connected to the battery assembly; and an outer terminal electrically connecting the battery assembly to an outer power or an outer load, wherein the circuit board includes a charge/discharge element for charging and discharging the battery assembly and a charge/discharge controller electrically connected to the battery assembly and the charge/discharge element, wherein the charge/discharge controller controls the charge and discharge of the battery assembly, and wherein a discharge cut-off voltage of the charge/discharge controller is predetermined as a voltage when LixSi present in the negative electrode during the discharge has an x value of less than or equal to about 1.25.Type: GrantFiled: September 23, 2016Date of Patent: May 8, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Hee Cho, Seong Woon Booh, Changhoon Jung, Eun Seog Cho
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Patent number: 9853378Abstract: According to example embodiments, a substrate for a power module includes first to third parts spaced apart from each other, where the third part surrounds the first and second parts, and a conductive layer on the first to third parts. A terminal of a first polarity is connected to the first part, and a terminal of a second polarity is connected to the second part. The first and second terminals may be spaced apart from each other and each have a coupling part, a body, and a contact part. The bodies of the first and second terminals may overlap each other. A power module may include the substrate.Type: GrantFiled: November 13, 2013Date of Patent: December 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Che-Heung Kim, Chang-Sik Kim, Seong-woon Booh
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Publication number: 20170331209Abstract: According to example embodiments, a substrate for a power module includes first to third parts spaced apart from each other, where the third part surrounds the first and second parts, and a conductive layer on the first to third parts. A terminal of a first polarity is connected to the first part, and a terminal of a second polarity is connected to the second part. The first and second terminals may be spaced apart from each other and each have a coupling part, a body, and a contact part. The bodies of the first and second terminals may overlap each other. A power module may include the substrate.Type: ApplicationFiled: August 2, 2017Publication date: November 16, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Che-heung KIM, Chang-sik KIM, Seong-woon BOOH
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Publication number: 20170093179Abstract: A battery assembly including: at least one rechargeable lithium battery including a negative electrode including a silicon-containing negative active material selected from silicon, a silicon-carbon composite, and a combination thereof, and a positive electrode including a positive active material; a circuit board electrically connected to the battery assembly; and an outer terminal electrically connecting the battery assembly to an outer power or an outer load, wherein the circuit board includes a charge/discharge element for charging and discharging the battery assembly and a charge/discharge controller electrically connected to the battery assembly and the charge/discharge element, wherein the charge/discharge controller controls the charge and discharge of the battery assembly, and wherein a discharge cut-off voltage of the charge/discharge controller is predetermined as a voltage when LixSi present in the negative electrode during the discharge has an x value of less than or equal to about 1.25.Type: ApplicationFiled: September 23, 2016Publication date: March 30, 2017Inventors: Yong Hee CHO, Seong Woon BOOH, Changhoon JUNG, Eun Seog CHO
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Patent number: 9520377Abstract: Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.Type: GrantFiled: June 23, 2014Date of Patent: December 13, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Won Yoon, Baik-woo Lee, Seong-woon Booh, Chang-mo Jeong
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Patent number: 9130095Abstract: Provided are a substrate for a power module having a uniform parallel switching characteristic and a power module including the same. The substrate for the power module includes a plurality of areas on which input terminals are mounted, an area on which an output terminal is mounted, a plurality of areas on which devices are mounted, and an area on which a plurality of control pins are mounted. The plurality of areas on which the devices are mounted are bilaterally symmetric about the area on which the plurality of control pins are mounted. The plurality of areas on which the input terminals are mounted, respectively, are provided into three areas spaced apart from each other and bilaterally symmetric to each other. The plurality of areas on which the device are mounted are bilaterally symmetric about the area on which the control pins are mounted.Type: GrantFiled: June 18, 2013Date of Patent: September 8, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Che-Heung Kim, Young-hun Byun, Seong-woon Booh
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Patent number: 9087833Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.Type: GrantFiled: November 29, 2013Date of Patent: July 21, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Baik-woo Lee, Seong-woon Booh
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Publication number: 20150115452Abstract: Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.Type: ApplicationFiled: June 23, 2014Publication date: April 30, 2015Inventors: Jeong-Won YOON, Baik-woo LEE, Seong-woon BOOH, Chang-mo JEONG
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Patent number: 8963325Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.Type: GrantFiled: January 11, 2013Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Baik-woo Lee, Young-hun Byun, Seong-woon Booh, Chang-mo Jeong
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Publication number: 20150001726Abstract: A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.Type: ApplicationFiled: November 22, 2013Publication date: January 1, 2015Applicant: Samsung Electronics Co., Ltd.Inventors: Baik-woo LEE, Seong-woon BOOH
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Patent number: 8872041Abstract: A multilayer laminate package and a method of manufacturing the same are provided. The multilayer laminate package includes a cavity layer, a non-cavity layer, an electronic component, and a metalized blind via. The cavity layer includes a first adhesive layer and two first circuit layers, which are stacked with the first adhesive layer between, and an opening. The non-cavity layer includes a second adhesive layer and a second circuit layer. The non-cavity layer is bonded to the cavity layer with the second adhesive layer so as to close one side of the opening. The electronic component is mounted in the opening and is electrically connected to the non-cavity layer exposed through the opening. The metalized blind via electrically connects the non-cavity layer to one of the circuit layers of the cavity layer.Type: GrantFiled: March 3, 2011Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Baik-Woo Lee, Ji-Hyuk Lim, Seong-Woon Booh
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Publication number: 20140218871Abstract: According to example embodiments, a substrate for a power module includes first to third parts spaced apart from each other, where the third part surrounds the first and second parts, and a conductive layer on the first to third parts. A terminal of a first polarity is connected to the first part, and a terminal of a second polarity is connected to the second part. The first and second terminals may be spaced apart from each other and each have a coupling part, a body, and a contact part. The bodies of the first and second terminals may overlap each other. A power module may include the substrate.Type: ApplicationFiled: November 13, 2013Publication date: August 7, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Che-Heung KIM, Chang-Sik KIM, Seong-woon BOOH
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Publication number: 20140151744Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.Type: ApplicationFiled: November 29, 2013Publication date: June 5, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Baik-woo LEE, Seong-woon BOOH
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Publication number: 20140120774Abstract: Provided are a substrate for a power module having a uniform parallel switching characteristic and a power module including the same. The substrate for the power module includes a plurality of areas on which input terminals are mounted, an area on which an output terminal is mounted, a plurality of areas on which devices are mounted, and an area on which a plurality of control pins are mounted. The plurality of areas on which the devices are mounted are bilaterally symmetric about the area on which the plurality of control pins are mounted. The plurality of areas on which the input terminals are mounted, respectively, are provided into three areas spaced apart from each other and bilaterally symmetric to each other. The plurality of areas on which the device are mounted are bilaterally symmetric about the area on which the control pins are mounted.Type: ApplicationFiled: June 18, 2013Publication date: May 1, 2014Inventors: Che-Heung KIM, Young-hun BYUN, Seong-woon BOOH
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Publication number: 20140021620Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.Type: ApplicationFiled: January 11, 2013Publication date: January 23, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Baik-woo LEE, Young-hun BYUN, Seong-woon BOOH, Chang-mo JEONG
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Patent number: 8477133Abstract: A method and apparatus for generating a three-dimensional FEM are provided. In the three-dimensional FEM generating method, a surface mesh is generated by meshing the surface of a three-dimensional model of a three-dimensional object. A projected contour is generated by projecting the three-dimensional model from one direction, and a projected contour mesh is generated by meshing the surface of the projected contour. A solid base mesh is generated by stacking solid elements on a base side formed of two-dimensional elements of the projected contour mesh. The surface mesh is substituted into the solid base mesh in alignment with the projected contour. A final solid mesh is generated by distinguishing solid elements surrounded by the surface mesh in the solid base mesh.Type: GrantFiled: November 17, 2004Date of Patent: July 2, 2013Assignee: Samsung Electronics Co., LtdInventors: Choong-Sik Kim, Seong-Woon Booh, Dong-Woo Lee, Jin-Woo Cho
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Patent number: 8466876Abstract: A terminal includes a lower housing; an upper housing slidably installed with respect to the lower housing; and a pressing member with both ends being supported by the lower and upper housings, respectively, for providing variable levels of pressure in diverse directions according to a sliding position of the upper housing with respect to the lower housing, wherein one end of the pressing member is movably linked to the lower housing. The small-sized pressing member provides a maximum level of pressure to facilitate the sliding movement of the upper housing with respect to the lower housing. Thus, space utilization can be improved.Type: GrantFiled: January 31, 2006Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ok Kwak, Eun-deok Bae, Dong-woo Lee, Ki-taek Kim, Seong-woon Booh, Jin-woo Cho
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Publication number: 20120024583Abstract: A multilayer laminate package and a method of manufacturing the same are provided. The multilayer laminate package includes a cavity layer, a non-cavity layer, an electronic component, and a metalized blind via. The cavity layer includes a first adhesive layer and two first circuit layers, which are stacked with the first adhesive layer between, and an opening. The non-cavity layer includes a second adhesive layer and a second circuit layer. The non-cavity layer is bonded to the cavity layer with the second adhesive layer so as to close one side of the opening. The electronic component is mounted in the opening and is electrically connected to the non-cavity layer exposed through the opening. The metalized blind via electrically connects the non-cavity layer to one of the circuit layers of the cavity layer.Type: ApplicationFiled: March 3, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Baik-Woo LEE, Ji-Hyuk LIM, Seong-Woon BOOH