Abstract: Disclosed is a slew rate control device using a switching capacitor which includes a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state.

Abstract: Disclosed is a slew rate control device using a switching capacitor which includes a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state.

Abstract: Disclosed is a voltage controlled oscillator which includes a first transistor in which a first terminal is connected to a first power supply, a body is connected to a gate, and a first output signal is output through a second terminal; a second transistor that is cross-coupled to the first transistor in such a manner that a first terminal is connected to the first power supply, a body connected to the second terminal of the first transistor is connected to a gate, and a second terminal is connected to the body of the first transistor, and that outputs a second output signal having an opposite phase to that of the first output signal through the second terminal; and a resonance filter in which a first terminal is connected to the second terminal of the first transistor and a second terminal is connected to the second terminal of the second transistor.