Patents by Inventor Seong Yeol SYN
Seong Yeol SYN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230252932Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 11631359Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: March 22, 2021Date of Patent: April 18, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20210209997Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 10957242Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: September 25, 2019Date of Patent: March 23, 2021Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20200020269Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 10467946Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: January 26, 2017Date of Patent: November 5, 2019Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Patent number: 9934746Abstract: A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.Type: GrantFiled: February 1, 2016Date of Patent: April 3, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Noboru Takeuchi, Min Soo Kang, Beom Jun Kim, Yoon Ho Kim, Seong Yeol Syn, Hong Woo Lee
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Publication number: 20170140698Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN
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Patent number: 9613582Abstract: Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.Type: GrantFiled: July 24, 2014Date of Patent: April 4, 2017Assignee: Samsung Display Co., Ltd.Inventors: Sung Man Kim, Jun Ho Song, Beom Jun Kim, Seong Yeol Syn, Young Je Cho
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Patent number: 9589519Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: GrantFiled: March 10, 2014Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Jung Hwan Hwang, Beom Jun Kim, Seong Yeol Syn, Bong-Jun Lee, You Mee Hyun
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Publication number: 20160358573Abstract: A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.Type: ApplicationFiled: February 1, 2016Publication date: December 8, 2016Inventors: Noboru TAKEUCHI, Min Soo KANG, Beom Jun KIM, Yoon Ho KIM, Seong Yeol SYN, Hong Woo LEE
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Publication number: 20160204136Abstract: A transistor and a liquid crystal display device having the same are provided. The transistor includes a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode.Type: ApplicationFiled: December 14, 2015Publication date: July 14, 2016Inventors: Noboru TAKEUCHI, Min-Soo KANG, Beom-Jun Kim, Yoon-Ho Kim, Seong-Yeol SYN, Hong-Woo Lee
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Publication number: 20150213746Abstract: Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.Type: ApplicationFiled: July 24, 2014Publication date: July 30, 2015Inventors: Sung Man KIM, Jun Ho SONG, Beom Jun KIM, Seong Yeol SYN, Young Je CHO
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Publication number: 20140267214Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.Type: ApplicationFiled: March 10, 2014Publication date: September 18, 2014Applicant: Samsung Display Co., Ltd.Inventors: Jung Hwan HWANG, Beom Jun KIM, Seong Yeol SYN, Bong-Jun LEE, You Mee HYUN