Abstract: An abnormal Internet Protocol Security (IPSec) packet control system and method utilizes IPSec configuration and session data to detect whether or not packets encrypted by an extended header are abnormal. The IPSec packet control system can include an extended header processing unit that receives an IPSec packet and extracts the data to be used in traffic control; check units for checking the packets in the stages of IPSec configuration and IPSec communication that receive the extracted data to determine whether or not the IPSec packet has passed; and a control unit that allows the IPSec to pass or to be blocked according to a determination result from the check units for checking the IPSec configuration and communication packets, where abnormal IPSec packets are blocked using the IPSec configuration and session tables without requiring them to be decrypted and encrypted.

Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Abstract: A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

Abstract: A method for testing a multi-chip package formed of different types of semiconductor devices, using an integrated burn-in test program which can reduce throughput time, reduce the possibility of error by an operator, and reduce workload. A multi-chip package is tested in burn-in equipment capable of applying a plurality of scan control clock signals. An integrated burn-in test program requires fewer burn-in test programs to be uploaded, fewer contact tests, and fewer bin sorting operations.

Abstract: A loader of semiconductor package burn-in test equipment allows a test socket to be commonly used for semiconductor packages of all sizes. The loader includes a vacuum suction head for picking semiconductor packages to be tested, and a package guider for ensuring that semiconductor packages of any size will be aligned with the test socket. As the semiconductor package is positioned over the test socket by the vacuum suction head of the loader, guide surfaces of the package guider are brought inwardly into guide positions at which the surfaces extend just beneath the vacuum suction head. Any semiconductor package that is not in alignment with the test socket while being held by the vacuum suction head is guided by the guides surfaces into alignment once the vacuum suction is turned off and the package falls from the vacuum suction head. Thus, the package guider serves as an adaptor, eliminating the need for several test sockets having respective adaptors for different sizes of semiconductor packages.

Abstract: A loader of semiconductor package burn-in test equipment allows a test socket to be commonly used for semiconductor packages of all sizes. The loader includes a vacuum suction head for picking semiconductor packages to be tested, and a package guider for ensuring that semiconductor packages of any size will be aligned with the test socket. As the semiconductor package is positioned over the test socket by the vacuum suction head of the loader, guide surfaces of the package guider are brought inwardly into guide positions at which the surfaces extend just beneath the vacuum suction head. Any semiconductor package that is not in alignment with the test socket while being held by the vacuum suction head is guided by the guides surfaces into alignment once the vacuum suction is turned off and the package falls from the vacuum suction head. Thus, the package guider serves as an adaptor, eliminating the need for several test sockets having respective adaptors for different sizes of semiconductor packages.