Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.

Abstract: A display device is provided, which includes a display main body, a support configured to support the display main body, and the support being made of a transparent material, and a stand coupled to a lower portion of the support, wherein the display main body is configured to receive a power supply through the stand and the support.

Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.

Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

Abstract: A display device is provided, which includes a display main body, a support configured to support the display main body, and the support being made of a transparent material, and a stand coupled to a lower portion of the support, wherein the display main body is configured to receive a power supply through the stand and the support.

Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

Abstract: A nonvolatile memory device includes a data generating unit for generating a first reference value randomly or pseudo-randomly according to a first program request to program data in a memory cell, a seed selecting unit for selecting at least one of a plurality of seeds using the first reference value, and a randomizer for generating randomized data by using the selected seed. The data generating unit regenerates the first reference value as a second reference value different from the first reference value when a second program request is made, and the seed selecting unit selects another seed using the second reference value.

Abstract: Performing a write operation or a read operation in a memory system may include compressing data of a first size unit, generating a plurality of types of Error Checking and Correction (ECC) information based on the compressed data, combining the compressed data and the plurality of types of ECC information in units of a second size, and writing the information combined in units of the second size into a memory device.

Abstract: An electronic device employing a polymeric anode with high work function.

Abstract: A method of performing a write operation or a read operation in a memory system includes compressing data of a first size unit, generating a plurality of types of Error Checking and Correction (ECC) information based on the compressed data, combining the compressed data and the plurality of types of ECC information in units of a second size, and writing the information combined in units of the second size into a memory device.

Abstract: A graphene electrode having a surface modified to have a high work function, and an electronic device including the same.

Abstract: An electronic device employing a polymeric anode with high work function.