Patents by Inventor Seonghyeog Choi

Seonghyeog Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240202067
    Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.
    Type: Application
    Filed: July 18, 2023
    Publication date: June 20, 2024
    Inventors: Seonghyeog CHOI, Changkyu Seol, Dong Kim, Inhoon Park, Jinsoo Lim, Youngdon Choi, Junghwan Choi
  • Publication number: 20240072992
    Abstract: A homomorphic encryption operator includes: a level configuration unit configured to set an encryption level by selecting a plurality of prime numbers of different values according to a scale factor condition used for multiplication of a homomorphic encryption operation and an increase/decrease condition for increasing or decreasing consecutively selected prime numbers, and a modular multiplication operator configured to perform lightweight modular multiplication using the selected plurality of prime numbers, wherein the level configuration unit includes: a level constructor configured to select prime number sets whose number have selected Hamming weights, respectively, based on the scale factor condition and the increase/decrease condition, and wherein the level configuration unit is further configured to configure the selected prime number sets with the encryption level using a prime number table.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Inventors: YOUNG SIK MOON, JIYOUP KIM, HANBYEUL NA, HONG RAK SON, SEONGHYEOG CHOI
  • Publication number: 20230187011
    Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
    Type: Application
    Filed: June 30, 2022
    Publication date: June 15, 2023
    Inventors: KANGSEOK LEE, GEUNYEONG YU, SEONGHYEOG CHOI, HONGRAK SON, YOUNGJUN HWANG
  • Publication number: 20230092380
    Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.
    Type: Application
    Filed: August 11, 2022
    Publication date: March 23, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog CHOI, Dong-Min SHIN, Hong Rak SON, Hyeonjong SONG, Yeongcheol JO
  • Publication number: 20230057932
    Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.
    Type: Application
    Filed: March 2, 2022
    Publication date: February 23, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanwoo NOH, Hyeonjong SONG, Wijik LEE, Hongrak SON, Dongmin SHIN, Seonghyeog CHOI
  • Patent number: 11456048
    Abstract: In a method of predicting a remaining lifetime of the nonvolatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, and at least one of the plurality of read operations is sequentially performed until read data stored in the nonvolatile memory device is successfully retrieved. Sequence class and error correction code (ECC) decoding information are generated. A life stage of the nonvolatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When it is determined that the nonvolatile memory device corresponds to a first life stage, a coarse prediction on the remaining lifetime of the nonvolatile memory device is performed. When it is determined that the nonvolatile memory device corresponds to a second life stage after the first life stage, a fine prediction on the remaining lifetime of the nonvolatile memory device is performed.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: September 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoon Yoon, Hyeonjong Song, Seonghyeog Choi, Hongrak Son
  • Publication number: 20220199185
    Abstract: In a method of predicting a remaining lifetime of the nonvolatile memory device, a read sequence is performed. The read sequence includes a plurality of read operations, and at least one of the plurality of read operations is sequentially performed until read data stored in the nonvolatile memory device is successfully retrieved. Sequence class and error correction code (ECC) decoding information are generated. A life stage of the nonvolatile memory device is determined based on at least one of the sequence class and the ECC decoding information. When it is determined that the nonvolatile memory device corresponds to a first life stage, a coarse prediction on the remaining lifetime of the nonvolatile memory device is performed. When it is determined that the nonvolatile memory device corresponds to a second life stage after the first life stage, a fine prediction on the remaining lifetime of the nonvolatile memory device is performed.
    Type: Application
    Filed: August 3, 2021
    Publication date: June 23, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jongyoon YOON, Hyeonjong SONG, Seonghyeog CHOI, Hongrak SON
  • Patent number: 11361832
    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunseung Han, Seonghyeog Choi, Youngsuk Ra, Hong Rak Son, Taehyun Song, Bohwan Jun
  • Patent number: 11189358
    Abstract: According to a method of controlling an operation of a nonvolatile memory device using machine learning, operating conditions of the nonvolatile memory device are determined by performing an inferring operation using a machine learning model. Training data that are generated based on feature information and error information are collected, where the error information indicate results of error correction code (ECC) decoding of the nonvolatile memory device. The machine learning model is updated by performing a learning operation based on the training data. Optimized operating conditions for individual user environments are provided by collecting training data in the storage system and performing the learning operation and the inferring operation based on the training data.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: November 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog Choi, Hongrak Son, Taehyun Song, Hyunsang Cho
  • Publication number: 20210202028
    Abstract: According to a method of controlling an operation of a nonvolatile memory device using machine learning, operating conditions of the nonvolatile memory device are determined by performing an inferring operation using a machine learning model. Training data that are generated based on feature information and error information are collected, where the error information indicate results of error correction code (ECC) decoding of the nonvolatile memory device. The machine learning model is updated by performing a learning operation based on the training data. Optimized operating conditions for individual user environments are provided by collecting training data in the storage system and performing the learning operation and the inferring operation based on the training data.
    Type: Application
    Filed: July 2, 2020
    Publication date: July 1, 2021
    Inventors: SEONGHYEOG CHOI, HONGRAK SON, TAEHYUN SONG, HYUNSANG CHO
  • Publication number: 20210202012
    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.
    Type: Application
    Filed: August 11, 2020
    Publication date: July 1, 2021
    Inventors: HYUNSEUNG HAN, SEONGHYEOG CHOI, YOUNGSUK RA, HONG RAK SON, TAEHYUN SONG, BOHWAN JUN
  • Patent number: 9837156
    Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changkyu Seol, Junjin Kong, JongHa Kim, Hyejeong So, Hong Rak Son, Seonghyeog Choi
  • Patent number: 9792990
    Abstract: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongjune Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong
  • Patent number: 9766973
    Abstract: A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonghyeog Choi, Changkyu Seol, Junjin Kong, Youngsuk Ra, Hong Rak Son
  • Patent number: 9646706
    Abstract: An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyejeong So, Junjin Kong, Changkyu Seol, Hong Rak Son, Seonghyeog Choi
  • Publication number: 20160276035
    Abstract: An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Inventors: HYEJEONG SO, JUNJIN KONG, CHANGKYU SEOL, HONG RAK SON, SEONGHYEOG CHOI
  • Publication number: 20160034349
    Abstract: A method of operating a nonvolatile memory device including a plurality of memory cells is provided. A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.
    Type: Application
    Filed: May 15, 2015
    Publication date: February 4, 2016
    Inventors: SEONGHYEOG CHOI, CHANGKYU SEOL, JUNJIN KONG, YOUNGSUK RA, HONG RAK SON
  • Publication number: 20160011807
    Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
    Type: Application
    Filed: March 6, 2015
    Publication date: January 14, 2016
    Inventors: Changkyu SEOL, Junjin KONG, JongHa KIM, Hyejeong SO, Hong Rak SON, Seonghyeog CHOI
  • Patent number: 9105359
    Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog Choi, Junjin Kong, Changkyu Seol, Hong Rak Son
  • Patent number: 8996947
    Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungsoo Chung, Junjin Kong, Changkyu Seol, Hong Rak Son, Pilsang Yoon, Seonghyeog Choi