Patents by Inventor Seonghyeog Choi

Seonghyeog Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837156
    Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changkyu Seol, Junjin Kong, JongHa Kim, Hyejeong So, Hong Rak Son, Seonghyeog Choi
  • Patent number: 9792990
    Abstract: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongjune Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong
  • Patent number: 9766973
    Abstract: A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonghyeog Choi, Changkyu Seol, Junjin Kong, Youngsuk Ra, Hong Rak Son
  • Patent number: 9646706
    Abstract: An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyejeong So, Junjin Kong, Changkyu Seol, Hong Rak Son, Seonghyeog Choi
  • Publication number: 20160276035
    Abstract: An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Inventors: HYEJEONG SO, JUNJIN KONG, CHANGKYU SEOL, HONG RAK SON, SEONGHYEOG CHOI
  • Publication number: 20160034349
    Abstract: A method of operating a nonvolatile memory device including a plurality of memory cells is provided. A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.
    Type: Application
    Filed: May 15, 2015
    Publication date: February 4, 2016
    Inventors: SEONGHYEOG CHOI, CHANGKYU SEOL, JUNJIN KONG, YOUNGSUK RA, HONG RAK SON
  • Publication number: 20160011807
    Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
    Type: Application
    Filed: March 6, 2015
    Publication date: January 14, 2016
    Inventors: Changkyu SEOL, Junjin KONG, JongHa KIM, Hyejeong SO, Hong Rak SON, Seonghyeog CHOI
  • Patent number: 9105359
    Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog Choi, Junjin Kong, Changkyu Seol, Hong Rak Son
  • Patent number: 8996964
    Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog Choi, Junjin Kong, Hong Rak Son, Pilsang Yoon
  • Patent number: 8996947
    Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungsoo Chung, Junjin Kong, Changkyu Seol, Hong Rak Son, Pilsang Yoon, Seonghyeog Choi
  • Publication number: 20140355348
    Abstract: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 4, 2014
    Inventors: Yongjune KIM, Hong Rak SON, Seonghyeog CHOI, Junjin KONG
  • Patent number: 8811080
    Abstract: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongjune Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong
  • Patent number: 8751900
    Abstract: A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong, Yongtaew Yim, Jaehong Kim, KyoungLae Cho, Wootae Chang
  • Patent number: 8711624
    Abstract: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghyeog Choi, Hong Rak Son, Junjin Kong, Jaehong Kim, KyoungLae Cho, Yong June Kim
  • Publication number: 20130326296
    Abstract: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding.
    Type: Application
    Filed: March 7, 2013
    Publication date: December 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SEONGHYEOG CHOI, JUNJIN KONG, CHANGKYU SEOL, HONG RAK SON
  • Publication number: 20130326314
    Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.
    Type: Application
    Filed: March 6, 2013
    Publication date: December 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SEONGHYEOG CHOI, JUNJIN KONG, HONG RAK SON, PILSANG YOON
  • Publication number: 20130173983
    Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.
    Type: Application
    Filed: August 30, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JUNGSOO CHUNG, JUNJIN KONG, CHANGKYU SEOL, HONG RAK SON, PILSANG YOON, SEONGHYEOG CHOI
  • Publication number: 20120069664
    Abstract: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Inventors: Yongjune KIM, Hong Rak SON, Seonghyeog CHOI, Junjin KONG
  • Publication number: 20120069657
    Abstract: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Inventors: Seonghyeog CHOI, Hong Rak Son, Junjin Kong, Jaehong Kim, KyoungLae Cho, Yong June Kim
  • Publication number: 20110283166
    Abstract: A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 17, 2011
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Yong June Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong, Yongtaew Yim, Jaehong Kim, KyoungLae Cho, Wootae Chang