Abstract: An artificial intelligence (AI) accelerator includes memory circuits configured to output weight data and vector data, a multiplication circuit/adder tree performing a multiplying/adding calculation on the weight data and the vector data to generate multiplication/addition result data, a first accumulator synchronized with an odd clock signal to perform an accumulative adding calculation on odd-numbered multiplication/addition result data of the multiplication/addition result data and a first latched data, and a second accumulator synchronized with an even clock signal to perform an accumulative adding calculation on even-numbered multiplication/addition result data of the multiplication/addition result data and a second latched data.

Abstract: A normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.

Abstract: An embodiment of the disclosed technology provides a semiconductor package including: a substrate; a first chip and a second chip stacked on the substrate, each of the first chip and the second chip including a slice command/address reception pad, a slice command/address transmission pad, a slice data pad, an input buffer connected to the slice command/address reception pad, an output buffer connected to the slice command/address transmission pad and an input/output buffer connected to the slice data pad; a first connection member connecting the slice command/address transmission pad of the first chip to the slice command/address reception pad of the second chip; and a second connection member connecting the slice data pad of the first chip to the slice data pad of the second chip.

Abstract: A semiconductor package includes a substrate; a first chip and a second chip stacked on the substrate, each including a first pad, a cell region, a first level serializer-deserializer connected to the first pad, a second level serializer-deserializer connected between the first level serializer-deserializer and the cell region and a second pad that is connected to a node between the first level serializer-deserializer and the second level serializer-deserializer; and a first connection member connecting the second pad of the first chip to the second pad of the second chip.

Abstract: A battery pack is configured to secure safety even when a thermal event occurs. The battery pack includes a battery module having at least one battery cell, a control module connected to the battery module and configured to manage the battery module, and a fire extinguishing tank containing a fire extinguishing agent, coupled to at least one of the battery module and the control module, and having a blocking member whose outer surface at least partially extends downward.

Abstract: A battery pack or the like configured to secure safety even when a thermal event occurs is disclosed. The battery pack according to an embodiment of the present disclosure includes a battery module having at least one battery cell, a control module connected to the battery module and configured to manage the battery module, and a fire extinguishing tank containing a fire extinguishing agent, coupled to at least one of the battery module and the control module, and having a rupture member configured to be ruptured under a predetermined condition so that the fire extinguishing agent comes out when the rupture member is ruptured.

Abstract: An adder circuit includes a negative number processing circuit configured to receive mantissa data and sign data of a plurality of floating point data and configured to output selected mantissa data, and an adder tree configured to perform an addition operation on the selected mantissa data to generate mantissa addition data. The negative number processing circuit is configured to output mantissa data of floating point data having a positive sign as the selected mantissa data, and to output an inverted mantissa data in which values of mantissa data of the floating point data having a negative sign are inverted as the selected mantissa data. And the adder tree is configured to perform the addition operation on the selected mantissa data with a number of “+1” operations equal to the number of the inverted mantissa data output from the negative number processing circuit.

Abstract: A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

Abstract: A battery pack includes a plurality of battery modules including module cases. Side surfaces of the module cases in which battery cells are accommodated face each other and a water injection hole is formed in a top surface of each of the module cases, and a fire extinguishing tank unit containing a fire extinguishing agent, located over the plurality of battery modules, and configured to supply the fire extinguishing agent only into a battery module in which a thermal event occurs from among the plurality of battery modules through the water injection holes.

Abstract: A battery pack includes a battery module having at least one battery cell, a control module connected to the battery module and configured to manage the battery module, a fire extinguishing tank containing a fire extinguishing agent and coupled to at least one of the battery module and the control module, and a side cover mounted on one side of the fire extinguishing tank and configured to guide electrical connection between the battery module and the control module.

Abstract: A battery pack ensures safety even when a thermal event occurs. A battery pack includes a battery module including one or more battery cells, a control module connected to the battery module to manage the battery module, and a fire extinguishing tank containing a fire extinguishing agent and coupled to at least one of the battery module and the control module.

Abstract: A battery pack includes a battery module including a water injection hole through which a fire extinguishing liquid can be supplied at an upper end portion and at least one drain hole through which the fire extinguishing liquid can be discharged at a lower end portion, a fire extinguishing tank unit containing the fire extinguishing liquid, located over the battery module, and configured to supply the fire extinguishing liquid to the battery module through the water injection hole, and a module supporter unit located under the battery module and supporting the battery module so that the battery module is located at a certain height from a ground. The module supporter unit includes a contaminated water storage container in which the fire extinguishing liquid dropping from the battery module through the drain hole is accommodated.

Abstract: An accumulator includes an exponent data latch circuit configured to output first exponent data of input data and second exponent data of latch data in synchronization with a first clock signal, a mantissa data latch circuit configured to output first mantissa data of the input data and second mantissa data of the latch data in synchronization with an edge of a second clock signal delayed by a delay time period later than an edge of the first clock signal, an exponent processing circuit configured to perform an exponent processing operation that generates first shift data and second shift data based on the first exponent data and the second exponent data transmitted from the exponent data latch circuit, and a mantissa processing circuit configured to shift the first mantissa data and the second mantissa data transmitted from the mantissa data latch circuit by the first shift data and the second shift data, respectively.

Abstract: A floating-point data operation circuit configured to perform an addition operation on first input data and second input data in floating-point format. The floating-point data operation circuit includes an exponent processing circuit configured to generate a number of first shift bits for first mantissa data of the first input data and a number of second shift bits for second mantissa data of the second input data using first exponent data of the first input data and second exponent data of the second input data. The exponent processing circuit includes an exponent subtraction circuit configured to generate and output exponent subtraction data by a subtraction operation and to generate and output a 2's complement of the exponent subtraction data, and a first selection output circuit configured to output first shift data and second shift data based on the most significant bit MSB value of the exponent subtraction data.

Abstract: A shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. The shift array circuit includes a plurality of shift arrays. The plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.

Abstract: A battery pack is advantageous for effective control and maintenance of thermal events. A battery pack according to one aspect of the present disclosure may include a battery module having one or more battery cells; a fire extinguishing tank holding a fire extinguishing liquid, disposed on top of the battery module and having a through hole formed therein; and a cover member installed in the through hole of the fire extinguishing tank and configured to open or close the through hole according to a change in internal pressure of the fire extinguishing tank.

Abstract: A multiplication and accumulation (MAC) operator includes a data input circuit configured to receive first operands and second operands and configured to output the first operands and third operands, a multiplication circuit configured to generate multiplication data by performing a multiplication operation on the first operands and the third operands, an addition circuit configured to generate multiplication addition data by performing an addition operation on the multiplication data, an accumulating circuit configured to generate accumulative data by performing an accumulative addition operation on the multiplication addition data and feedback data, and an error correction circuit configured to detect a computational error in the accumulative data when a computational error occurs, and configured to output, as MAC result data, accumulative data having the computational error corrected.

Abstract: A semiconductor package includes a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and the time point at which the internal data are output become identical with each other, and configured to program the stored test codes when the training operation is terminated.

Abstract: A multiplication and accumulation (MAC) operator includes a residue number generating circuit configured to generate a plurality of weight residue number data for weight data and a plurality of vector residue number data for the vector data by using a plurality of divisors, a multiplication circuit configured to generate a plurality of residue number multiplication data by performing a multiplication operation on the weight residue number data and the vector residue number data, an addition circuit configured to generate residue number multiplication addition data by performing an addition operation on the multiplication data, an accumulating circuit configured to generate residue number accumulation data by performing an accumulation operation on the residue number multiplication addition data and latch data, and a mixed radix conversion circuit configured to generate the MAC result data by using the divisors and the residue number accumulation data that is transmitted by the accumulating circuit.