Abstract: A secondary battery includes an electrode assembly having a positive electrode provided with a positive electrode tab, a separator, and a negative electrode provided with a negative electrode tab, the positive electrode, the separator, and the negative electrode being wound, the electrode assembly having a core part at a center thereof; a can configured to receive the electrode assembly therein, the negative electrode tab being connected to the can; a cap assembly coupled to an opening of the can, the positive electrode tab being connected to the cap assembly; and a reinforcing member provided on an end of the separator exposed beyond the positive electrode or the negative electrode to prevent heat of the positive electrode tab or the negative electrode tab from being transferred to the separator.

Abstract: A transmitting and receiving circuit may include a first CMOS inverter configured to receive a first power supply signal and a first input signal. The transmitting and receiving circuit may include a first calculation amplifier including a non-inverted input terminal connected to an output terminal of the first CMOS inverter, and a first resistor connected between the output terminal of the first calculation amplifier and a first node. The output terminal of the first calculation amplifier and an inverted input terminal of the first calculation amplifier may be connected to each other. A first output signal may have a level smaller than that of the first input signal and may be output to the first node.

Abstract: A power supply apparatus includes first through M-th switching regulators, first through N-th multiplexers, and first through N-th linear regulators, where each of M and N is a natural number greater than or equal to two. The first through M-th switching regulators generate first through M-th reference power signals using an input power signal. The first through N-th multiplexers select one of the first through M-th reference power signals, in response to a power selection signal, to provide first through N-th selection power signals. The first through N-th linear regulators generate first through N-th output power signals using the first through N-th selection power signals. The first through N-th linear regulators are connected to the first through N-th multiplexers, respectively.

Abstract: A power supply apparatus includes first through M-th switching regulators, first through N-th multiplexers, and first through N-th linear regulators, where each of M and N is a natural number greater than or equal to two. The first through M-th switching regulators generate first through M-th reference power signals using an input power signal. The first through N-th multiplexers select one of the first through M-th reference power signals, in response to a power selection signal, to provide first through N-th selection power signals. The first through N-th linear regulators generate first through N-th output power signals using the first through N-th selection power signals. The first through N-th linear regulators are connected to the first through N-th multiplexers, respectively.

Abstract: A test system including a test device configured to transmit an input signal and a control signal to at least one complementary metal-oxide semiconductor (CMOS) image sensor via a probe card, and an interface board configured to map the probe card and the test device. The interface board includes an output receiver configured to receive an image signal from the at least one CMOS image sensor and transform the image signal into image data.

Abstract: A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.