Patents by Inventor Seong-rae Cho

Seong-rae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939651
    Abstract: Provided is an Al—Fe-alloy plated steel sheet for hot forming, having excellent TWB welding characteristics since excellent hardness uniformity of a TWB weld zone after hot forming is obtained by suitably controlling a batch annealing condition, after plating Al, such that an Al—Fe-alloy layer is formed; a hot forming member; and manufacturing methods therefor.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 26, 2024
    Assignee: POSCO CO., LTD
    Inventors: Seong-Woo Kim, Jin-Keun Oh, Yeol-Rae Cho, Hyeon-Jeong Shin
  • Publication number: 20210360798
    Abstract: A printed circuit board includes a rigid part including a central insulating layer for insulation, inner copper foil layers including a first conductive circuit portion, outer insulating layers for insulation, and outer copper foil layers including a second conductive circuit portion, wherein ones of the inner copper foil layers, the outer insulating layers, and the outer copper foil layers are symmetrically positioned on opposite sides of the central insulating layer and are sequentially laminated, and a flexible part formed by selectively removing a portion of the rigid part up to one side of the central insulating layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: November 18, 2021
    Inventors: SeungWoo Choi, Seong-Rae Cho, Seoung-Won Kim, Hyeok-Jin Jeong
  • Patent number: 5721740
    Abstract: A flip-flop controller including a clock controller for enabling or disabling a clock signal in response to a clock enabling signal and one or more flip-flops for selectively latching a function mode signal or scan test mode signal in response to a mode selection signal while being synchronous with the clock signal, is provided. As a result, a test vector is easily generated, fault coverage is increased to a desired degree using relatively few test vectors. Also, power consumption can be reduced by disabling the unnecessary portion of the clock signal applied to the flip-flop.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: February 24, 1998
    Assignee: Samsung Electronocs Co., Ltd.
    Inventors: Kab-ju Moon, Seong-rae Cho, Hyuk-sang Kwon