Abstract: This disclosure describes systems, methods, and devices related to optical proximity corrections to an integrated circuit photomask. A method may include identifying a first contour of a first adjacent polygon of a photomask predicted for a first polygon of an integrated circuit, the first contour excluding a first corner formed by a first edge and a second edge of the first polygon; identifying a second contour of a second adjacent polygon of a photomask predicted for a second polygon of the integrated circuit, the second contour excluding a second corner formed by a third edge and a fourth edge of the second polygon; generating a fast contour prediction based on corner rounding associated with the first contour and the second contour; and generating, based on the fast contour prediction, a minimum distance between the first contour and the second contour, the minimum distance associated with the optical proximity corrections.

Abstract: This disclosure describes systems, methods, and devices related to optical proximity corrections to an integrated circuit photomask. A method may include identifying a first contour of a first adjacent polygon of a photomask predicted for a first polygon of an integrated circuit, the first contour excluding a first corner formed by a first edge and a second edge of the first polygon; identifying a second contour of a second adjacent polygon of a photomask predicted for a second polygon of the integrated circuit, the second contour excluding a second corner formed by a third edge and a fourth edge of the second polygon; generating a fast contour prediction based on corner rounding associated with the first contour and the second contour; and generating, based on the fast contour prediction, a minimum distance between the first contour and the second contour, the minimum distance associated with the optical proximity corrections.

Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.

Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

Abstract: An antenna using a slot formed by assembling a mobile terminal case and a metal structure (e.g., a bracket), is disclosed. The antenna reduces deterioration of antenna performance resulting from frequency interference or electromagnetic interference. The antenna can be used in various frequency bands.

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

Abstract: A scattered light point spread function is measured for use in fabricating microelectronic and micromechanical devices using photolithography. In one example, a photosensitive layer of a microelectronic substrate is exposed through a test mask, the test mask having a series of differently sized patterns, each pattern surrounding a central monitor feature, the differently sized patterns each being evenly distributed about its respective central monitor feature. An indication of the exposure of the photosensitive layer is measured for a plurality of the series of differently sized patterns. The exposure indication is compared to the pattern size. The comparison is fitted to a function and the function is applied in correcting photolithography mask layouts.

Abstract: A scattered light point spread function is measured for use in fabricating microelectronic and micromechanical devices using photolithography. In one example, a photosensitive layer of a microelectronic substrate is exposed through a test mask, the test mask having a series of differently sized patterns, each pattern surrounding a central monitor feature, the differently sized patterns each being evenly distributed about its respective central monitor feature. An indication of the exposure of the photosensitive layer is measured for a plurality of the series of differently sized patterns. The exposure indication is compared to the pattern size. The comparison is fitted to a function and the function is applied in correcting photolithography mask layouts.

Abstract: Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.

Abstract: Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.

Abstract: This application includes techniques for applying image imbalance compensation by aperture sizing and optical proximity approximation in designing a phase mask.

Abstract: A method for performing scanned defect inspection of a collection of contiguous areas using a specified false-alarm-rate and capture-rate within an inspection system that has characteristic seek times between inspection locations. The multi-stage method involves setting an increased false-alarm-rate for a first stage of scanning, wherein subsequent stages of scanning inspect only the detected areas of probable defects at lowered values for the false-alarm-rate. For scanning inspection operations wherein the seek time and area uncertainty is favorable, the method can substantially increase inspection throughput.