Abstract: A display device may include: a gate driver configured to apply a plurality of gate signals to each of a plurality of gate lines; a source driver configured to generate a plurality of first data signals corresponding to each of a plurality of source lines; and an interpolation circuit configured to: receive the plurality of first data signals from the source driver; and provide a second data signal, obtained by interpolating a first data signal corresponding to a first source line among the plurality of source lines and a first data signal corresponding to a third source line among the plurality of source lines, to a second source line between the first source line and the third source line.

Abstract: A display device is provided. The display device includes: a pixel array including pixels connected to gate lines and source lines; and a driving circuit configured to: apply gate signals to the gate lines and provide data signals to the source lines during a first scan period such that horizontal periods of the gate signals do not overlap each other, and apply the gate signals to first gate lines, of the gate lines, connected to pixels in a first area of the pixel array in a different manner from second gate lines, of the gate lines, connected to pixels in a second area of the pixel array for a portion of a second scan period, provide the data signals to the source lines, and maintain a low-biased state or an off state for a remaining portion of the second scan period.

Abstract: A display device is provided. The display device includes: a pixel array including pixels connected to gate lines and source lines; and a driving circuit configured to: apply gate signals to the gate lines and provide data signals to the source lines during a first scan period such that horizontal periods of the gate signals do not overlap each other, and apply the gate signals to first gate lines, of the gate lines, connected to pixels in a first area of the pixel array in a different manner from second gate lines, of the gate lines, connected to pixels in a second area of the pixel array for a portion of a second scan period, provide the data signals to the source lines, and maintain a low-biased state or an off state for a remaining portion of the second scan period.

Abstract: A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region.

Abstract: A display driving circuit in accordance with the inventive concepts may include a source amplifier. The source amplifier may include an output transistor configured to amplify an input signal to generate an output signal, and charge a source line of a display panel using the output signal. The source amplifier may include an output transistor switch configured to control the output transistor, and a switch control block configured to receive configuration bits including on/off time information of the output transistor switch to generate a switch control signal. The on/off time information includes information for turning on the output transistor switch in synchronization with a horizontal synchronous signal associated with the display panel, and information for turning off the output transistor switch at a time when the source line of the display panel is charged to a desired charge level.

Abstract: A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region.

Abstract: A display driving circuit includes a frame buffer that stores a plurality of pieces of line data, and a buffer controller. The buffer controller receives a data packet, and outputs first line data included in the data packet or second line data stored in the frame buffer as grayscale data based on flag information included in the data packet.

Abstract: A driving apparatus and a display driving system. The driving apparatus includes a first amplification unit receiving a first signal and outputting a driving signal of a positive polarity voltage with respect to a reference voltage, a second amplification unit receiving a second signal and outputting a driving signal of a negative polarity voltage with respect to the reference voltage, and a controller for determining a chopping signal applied to a chopping terminal of the second amplification unit such that an offset polarity of an output voltage of the first amplification unit and an offset polarity of an output voltage of the second amplification unit are the same.

Abstract: A display driving circuit in accordance with the inventive concepts may include a source amplifier. The source amplifier may include an output transistor configured to amplify an input signal to generate an output signal, and charge a source line of a display panel using the output signal. The source amplifier may include an output transistor switch configured to control the output transistor, and a switch control block configured to receive configuration bits including on/off time information of the output transistor switch to generate a switch control signal. The on/off time information includes information for turning on the output transistor switch in synchronization with a horizontal synchronous signal associated with the display panel, and information for turning off the output transistor switch at a time when the source line of the display panel is charged to a desired charge level.

Abstract: A display device includes a display panel having pixels arranged at intersections of source lines and gate lines, a plurality of source drivers configured to dispersedly output image data signals to the source lines in response to source control signals and a data packet, a plurality of gate drivers configured to drive gate lines in response to gate control signals so as to be connected with pixels corresponding to the source lines, and a timing controller configured to output the data packet, the source control signals, and the gate control signals. At least one of the plurality of source drivers is configured to output carry information associated with an output of the image data signals, and at least another of the plurality of source drivers is configured to output the image data signals in response to the carry information.

Abstract: A driving apparatus and a display driving system. The driving apparatus includes a first amplification unit receiving a first signal and outputting a driving signal of a positive polarity voltage with respect to a reference voltage, a second amplification unit receiving a second signal and outputting a driving signal of a negative polarity voltage with respect to the reference voltage, and a controller for determining a chopping signal applied to a chopping terminal of the second amplification unit such that an offset polarity of an output voltage of the first amplification unit and an offset polarity of an output voltage of the second amplification unit are the same.

Abstract: Display devices are provided. The display devices may include a source driver chip between a printed circuit board and a display panel. The source driver chip may overlap a plurality of bypass lines that are connected to the printed circuit board and the display panel.