Patents by Inventor Seon-Hyang You

Seon-Hyang You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120199964
    Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 9, 2012
    Inventors: JUNG-DO LEE, Hale-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You
  • Patent number: 8184449
    Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Do Lee, Hak-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You
  • Publication number: 20120068350
    Abstract: A semiconductor package, an electronic device, and an electronic system employing the same are provided. The semiconductor package includes a printed circuit board (PCB) and a semiconductor chip structure. A first PCB land region is provided on a first surface of the PCB. A plurality of first chip land regions are provided on a first surface of the semiconductor chip structure which faces the first surface of the PCB. A first connection structure for electrically connecting the first PCB land region to the plurality of first chip land regions is provided.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 22, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tong-Suk Kim, Woo-Jae Kim, Yun-Seok Choi, Seon-Hyang You
  • Publication number: 20090085185
    Abstract: A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Kyoon BYUN, Tae-Hun KIM, Sang-Uk HAN, Jung-Do LEE, Seon-Hyang YOU
  • Publication number: 20090067143
    Abstract: An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 12, 2009
    Inventors: Jung-Do Lee, Hak-Kyoon Byun, Tae-Hun Kim, Sang-Uk Han, Seon-Hyang You