Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction; first and second lower channel layers in a first region and a second region of the active pattern, respectively; first and second upper channel layers on the first and second lower channel layers, respectively; a first source/drain pattern connected to the first and second lower channel layers; an isolation insulating layer on surfaces of the first source/drain pattern in the second direction, where a thickness of opposing edge portions of the isolation insulating layer when viewed in cross section along the first direction is smaller than a thickness of a central portion therebetween; a second source/drain pattern connected to the first and second upper channel layers; and an interlayer insulating layer on the second source/drain patterns and on the isolation insulating layer.

Abstract: A photolithograph method is provided. The photolithograph method may include forming a photoresist pattern on a substrate and conformally forming a liner layer on the photoresist pattern, wherein the forming of the liner layer includes a deposition process of reacting an initiator and a monomer with each other, the monomer includes multiple bonds between carbon atoms, the initiator includes a material that forms a radical by thermal decomposition, a copolymer is formed by an initiating reaction between the radical and the monomer, and the liner layer includes the copolymer.

Abstract: A semiconductor device includes a memory cell structure on a substrate, and a dummy structure on a side of the memory cell structure. The memory cell structure includes a memory stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, channel structures penetrating through the memory stack structure and contacting the substrate, and first separation structures penetrating through the memory stack structure and extending in the first direction to separate the gate electrodes from each other in a second direction. The dummy structure includes dummy stack structures spaced apart from the memory stack structure and including first insulating layers and dummy gate electrodes alternately stacked, dummy channel structures penetrating through the dummy stack structures, and second separation structures penetrating through the dummy stack structures and extending in the second direction to separate the dummy gate electrodes from each other in the first direction.