Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A display panel of a display device is divided into a first display region and a second display region. The second display region includes a boundary region adjacent to the first display region and a non-boundary region opposite to the first display region with respect to the boundary region. The driving controller outputs the voltage control signal, such that the first voltage in a first high voltage level and the second voltage in a first low voltage level are generated when the first display region is driven. The driving controller outputs the voltage control signal, such that the first voltage in a second high voltage level lower than the first high voltage level and the second voltage in a second low voltage level higher than the first low voltage level are generated, when the non-boundary region of the second display region is driven.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A display device includes a support plate including first to third regions, and a display panel divided into first to third display regions overlapping the first to third regions, and including light emitting elements (LEs) and pixel circuits (PCs). The second display region includes a first partial region in which first and second PCs, and a first LE are disposed, and a second partial region in which a second LE is disposed. The third display region includes a third partial region in which third and fourth PCs, and a third LE are disposed to overlap a first support portion of the third region, and a fourth partial region in which a fourth LE is disposed to overlap each opening in the third region. A first separation distance between the second PC and the second LE is less than a second separation distance between the fourth PC and the fourth LE.

Abstract: A display panel of a display device is divided into a first display region and a second display region. The second display region includes a boundary region adjacent to the first display region and a non-boundary region opposite to the first display region with respect to the boundary region. The driving controller outputs the voltage control signal, such that the first voltage in a first high voltage level and the second voltage in a first low voltage level are generated when the first display region is driven. The driving controller outputs the voltage control signal, such that the first voltage in a second high voltage level lower than the first high voltage level and the second voltage in a second low voltage level higher than the first low voltage level are generated, when the non-boundary region of the second display region is driven.

Abstract: A display device includes: a substrate; and a semiconductor layer including a driving transistor and a fourth transistor on the substrate, wherein a first electrode of the driving transistor is connected to a driving voltage line to receive a driving voltage, a first electrode of the fourth transistor is connected to a first initialization voltage line to receive a first initialization voltage, a second electrode of the fourth transistor is connected to a gate electrode of the driving transistor, a low doping region is between a channel of the fourth transistor and the first electrode of the fourth transistor, and a low doping region is not between the channel of the further transistor and the second electrode of the fourth transistor.

Abstract: A display panel includes a base layer including a boundary area and a pixel area, a pixel circuit that overlaps the pixel area, a plurality of insulating layers which includes at least a first insulating layer and in which an opening overlapping the boundary area is defined, a first signal line that is disposed on the first insulating layer and that overlaps the boundary area and the pixel area, an organic layer including a first portion that fills the opening, and a light-emitting element disposed over the plurality of insulating layers and electrically connected to the pixel circuit. The opening includes a first area that overlaps the first signal line and has a first depth and a second area having a second depth greater than the first depth.

Abstract: A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.

Abstract: A pixel includes a light emitting element, a data write switching element, a driving switching element, a light emitting element initialization switching element and a boosting capacitor. The data write switching element is configured to receive a data voltage from the outside. The driving switching element is configured to apply a driving current to the light emitting element based on the data voltage. The light emitting element initialization switching element is configured to apply an initialization voltage to a first electrode of the light emitting element. The boosting capacitor includes a first electrode connected to a control electrode of the light emitting element initialization switching element and a second electrode connected to an output electrode of the data write switching element.

Abstract: A display device includes: scan lines extending in a first direction; data lines extending in a second direction intersecting the first direction and receiving data voltages; first driving voltage lines extending in the second direction and receiving a first driving voltage; second driving voltage lines extending in the second direction and receiving a second driving voltage different from the first driving voltage; and pixels connected to the scan and data lines. Each of the pixels includes first, second, and third subpixels arranged in the first direction. The first driving voltage lines and the second driving voltage lines are alternately arranged in the first direction. A location of the first driving voltage line in a first pixel differs from a location of the second driving voltage line in a second pixel. The second pixel is adjacent to the first pixel in the first direction.

Abstract: A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A pixel includes a light emitting element, a data write switching element, a driving switching element, a light emitting element initialization switching element and a boosting capacitor. The data write switching element is configured to receive a data voltage from the outside. The driving switching element is configured to apply a driving current to the light emitting element based on the data voltage. The light emitting element initialization switching element is configured to apply an initialization voltage to a first electrode of the light emitting element. The boosting capacitor includes a first electrode connected to a control electrode of the light emitting element initialization switching element and a second electrode connected to an output electrode of the data write switching element.

Abstract: A driving circuit includes: a plurality of scan stages each corresponds to a plurality of scan lines, receives clock signals and a carry signal, and outputs a scan signal; and a plurality of masking circuits corresponding to some scan stages, respectively, among the scan stages. each masking circuit outputs one of the scan signal output from a corresponding scan stage and a first voltage as a masking carry signal in response to a masking signal. A j-th scan stage receives a scan signal output from a (j?a)th scan stage as the carry signal when the (j?a)th scan stage is not one of the some first scan stages, and the masking carry signal output from a masking circuit corresponding to the (j?a)th scan stage as the carry signal when the (j?a)th scan stage is one of the some first scan stages.

Abstract: A driving circuit includes: a plurality of scan stages each corresponds to a plurality of scan lines, receives clock signals and a carry signal, and outputs a scan signal; and a plurality of masking circuits corresponding to some scan stages, respectively, among the scan stages. each masking circuit outputs one of the scan signal output from a corresponding scan stage and a first voltage as a masking carry signal in response to a masking signal. A j-th scan stage receives a scan signal output from a (j?a)th scan stage as the carry signal when the (j?a)th scan stage is not one of the some first scan stages, and the masking carry signal output from a masking circuit corresponding to the (j?a)th scan stage as the carry signal when the (j?a)th scan stage is one of the some first scan stages.

Abstract: A display device includes: a substrate including a main display portion, edge portions disposed at edges of the main display portion and including rounded corners, first side portions bent from the edge portions, and second side portions bent from the main display portion; scan lines and data lines that are disposed on the substrate; transistors connected to the scan lines and the data lines; and a data voltage transmission line connected to data lines that are disposed in the first side portions and the edge portions.

Abstract: A display device includes: scan lines extending in a first direction; data lines extending in a second direction intersecting the first direction and receiving data voltages; first driving voltage lines extending in the second direction and receiving a first driving voltage; second driving voltage lines extending in the second direction and receiving a second driving voltage different from the first driving voltage; and pixels connected to the scan and data lines. Each of the pixels includes first, second, and third subpixels arranged in the first direction. The first driving voltage lines and the second driving voltage lines are alternately arranged in the first direction. A location of the first driving voltage line in a first pixel differs from a location of the second driving voltage line in a second pixel. The second pixel is adjacent to the first pixel in the first direction.

Abstract: The present disclosure relates to an electronic device. A storage device includes a memory device configured to include a plurality of memory cells and a memory controller configured to determine a read voltage for a read operation to be performed on the memory device according to whether the read operation is a cache read operation.