Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Abstract: A level shifter for level shifting an input signal from a first level to an output signal having a second level includes an operation range extension portion configured to extend an input range of the level shifter and to generate a first extension control signal in response to the input signal and a second extension control signal in response to an inverted version of the input signal, an output control portion configured to generate an output control signal in response to the input signal, the first extension control signal, and the output signal, and an output portion configured to generate the output signal in response to the inverted version of the input signal, the second extension control signal, and an output control signal.

Abstract: A Multi Chip Package (MCP) and a related method for enabling a cell in the MCP are provided. In one embodiment, the MCP comprises a first memory device and a second memory device storing repair address information about the first memory device.

Abstract: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: A speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Abstract: An anti-fuse circuit includes an anti-fuse device and an electric field control unit. The anti-fuse device is formed having a MOS structure including a first junction, a second junction and a gate terminal. The electric field control unit performs a control operation so that an electric field is formed in the anti-fuse device at the time of an anti-fusing operation. Electric fields formed at the first and second junctions of the anti-fuse device are separately controlled, so that breakdown can occur at two points. Further, the gate terminal of the anti-fuse device is implemented in the form of a band-shaped closed circuit.

Abstract: A level shifter for level shifting an input signal from a first level to an output signal having a second level includes an operation range extension portion configured to extend an input range of the level shifter and to generate a first extension control signal in response to the input signal and a second extension control signal in response to an inverted version of the input signal, an output control portion configured to generate an output control signal in response to the input signal, the first extension control signal, and the output signal, and an output portion configured to generate the output signal in response to the inverted version of the input signal, the second extension control signal, and an output control signal.

Abstract: In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.