Abstract: A bus system including first and second blocks. The bus system is configured such that data may be transferred at the first block at the same time that data may be transferred at the second block.

Abstract: An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator. The interrupt source allocation unit may output one or more interrupt source signals based on one or more priorities, and may allow a user to move an individual interrupt source signal without moving other interrupt source signals. The interrupt pending register may set bits in one or more registers corresponding to the interrupt source signals. The control register may control and transmit the interrupt source signals corresponding to the set bits. The priority register may determine the priorities of the interrupt source signals. The interrupt request signal generator may output an interrupt request signal in response to one or more interrupt source signals received from the priority register.

Abstract: An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator. The interrupt source allocation unit may output one or more interrupt source signals based on one or more priorities, and may allow a user to move an individual interrupt source signal without moving other interrupt source signals. The interrupt pending register may set bits in one or more registers corresponding to the interrupt source signals. The control register may control and transmit the interrupt source signals corresponding to the set bits. The priority register may determine the priorities of the interrupt source signals. The interrupt request signal generator may output an interrupt request signal in response to one or more interrupt source signals received from the priority register.

Abstract: A bus system including first and second blocks. The bus system is configured such that data may be transferred at the first block at the same time that data may be transferred at the second block.

Abstract: A digital signal processor includes an execution unit separated into an arithmetic unit, a multiplier unit, a logic unit, a shift unit and a log unit, to implement CCITT G721 ADPCM algorithm with a relatively small size, which reduces the system cost. Also, since the digital signal processor primarily takes into consideration of low power consumption, it is applicable to a mobile communication system. Also, the digital signal processor is capable of implementing easily other ADPCM rates and algorithms as well as the ADPCM algorithm by modifying only the program of an instruction ROM.