Patents by Inventor Seoung Jeong Lee

Seoung Jeong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY
    Publication number: 20130282991
    Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
    Type: Application
    Filed: March 25, 2013
    Publication date: October 24, 2013
    Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
  • Method and system for improving serial port memory communication latency and reliability
    Patent number: 8407427
    Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 26, 2013
    Assignee: Silicon Image, Inc.
    Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
  • METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY
    Publication number: 20100106917
    Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 29, 2010
    Inventors: Alan Ruberg, Seoung Jeong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy