Patents by Inventor Seoung-Woo KUK

Seoung-Woo KUK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11415369
    Abstract: The present invention provides a crucible for melting and casting a metal fuel, which includes a reaction preventing layer including: LaYO3; or ZrO2 containing a Y2O3 stabilizer at 5 to 10 wt %, and a method of melting and casting a metal fuel using the same.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 16, 2022
    Assignee: KOREA ATOMIC ENERGY RESEARCH INSTITUTE
    Inventors: Seoung Woo Kuk, Kyung Chai Jeong, Seok Jin Oh, Jeong-Yong Park, Ki Hwan Kim, Yoon Myeng Woo, Seung Uk Mun, Seong-Jun Ha
  • Publication number: 20210148637
    Abstract: The present invention provides a crucible for melting and casting a metal fuel, which includes a reaction preventing layer including: LaYO3; or ZrO2 containing a Y2O3 stabilizer at 5 to 10 wt %, and a method of melting and casting a metal fuel using the same.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 20, 2021
    Inventors: Seoung Woo KUK, Kyung Chai Jeong, Seok Jin Oh, Jeong-Yong Park, Ki Hwan Kim, Yoon Myeng Woo, Seung Uk Mun, Seong-Jun Ha
  • Patent number: 8519471
    Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: August 27, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seoung-Woo Kuk, Kang-Jae Lee
  • Publication number: 20110147823
    Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 23, 2011
    Inventors: Seoung-Woo KUK, Kang-Jae Lee