Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction.

Abstract: A direct memory access (DMA) controller comprises template storage circuitry to store at least one DMA template indicative of a DMA data access pattern. Each DMA template comprises enable indications settable to an enable state or a disable state. In response to a DMA command associated with a source address, a destination address, a source DMA template, and a destination DMA template, DMA control circuitry generates a set of DMA memory access requests to copy data from source memory system locations to destination memory system locations. The source/destination memory system locations are selected to have addresses which are offset relative to the source/destination address by offset amounts corresponding to positions of enable indications set to the enable state within the source/destination DMA template. The source/destination DMA templates allow irregular patterns of DMA accesses to be controlled in fewer DMA commands.

Abstract: A data processing apparatus includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus-2. The mapping parameters may be fixed or software programmable.

Abstract: An apparatus includes processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier and configuration application circuitry applies the set of memory transaction parameters in respect of memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation of a resource used by a memory system in handling the memory transaction that identifies the partition identifier. Also provided is an apparatus that comprises processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters and associated partition identifiers.

Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction.

Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

Abstract: An integrated circuit comprises first and second power domains, and a message handling unit to control passing of messages sent from a sender device in the first power domain to a receiver device in the second power domain. The message handling unit writes messages sent from the sender device to a message storage area, provided in the second power domain. The message handling unit is responsive to a message send request from the sender device requesting sending of at least one message to the receiver device when at least one device in the second power domain is in a quiescent state, to transmit a wakeup request to a second domain power controller to request that said at least one device in the second power domain transitions from the quiescent state to an awake state.

Abstract: An integrated circuit (2) has first and second domains (4). The first domain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.

Abstract: An integrated circuit (2) has first and second domains (4). The first omain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.

Abstract: Clock signal control circuitry comprises a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal; a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; in which the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.

Abstract: An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is cur

Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

Abstract: An integrated circuit comprises first and second power domains, and a message handling unit to control passing of messages sent from a sender device in the first power domain to a receiver device in the second power domain. The message handling unit writes messages sent from the sender device to a message storage area, provided in the second power domain. The message handling unit is responsive to a message send request from the sender device requesting sending of at least one message to the receiver device when at least one device in the second power domain is in a quiescent state, to transmit a wakeup request to a second domain power controller to request that said at least one device in the second power domain transitions from the quiescent state to an awake state.

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

Abstract: A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.

Abstract: An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is cur

Abstract: Methods and apparatus for adaptive encoding of data such as for example video data. In one exemplary embodiment, a real-time video encoder is disclosed that changes video encoding processes to produce the best quality encoded video while maintaining a target encoding frame rate, according to one or more operating constraints.

Abstract: Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device.

Abstract: Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device.