Patents by Inventor Sepideh NOURI

Sepideh NOURI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087647
    Abstract: Present implementations are directed to nonvolatile memory devices with charge trap transistor structures. Example implementations can include a method of memory storage, by programming a first data node operatively coupled to a first charge trap transistor to a first level above a threshold, decreasing, below the threshold, a first voltage at the first charge trap transistor, increasing, above the threshold, the first voltage at the first charge trap transistor, and reprogramming, the first data node to the first level, in response to an interruption of the first voltage at the first charge trap transistor caused by the decreasing and the increasing.
    Type: Application
    Filed: January 28, 2022
    Publication date: March 14, 2024
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sepideh NOURI, Subramanian IYER
  • Publication number: 20230178146
    Abstract: A method for changing functionality of an integrated circuit or improving performance of an integrated circuit, may include changing a threshold voltage of at least one charge trap transistor (CTT) in a nonvolatile multi-time programmable fashion. The at least one CTT may be fabricated using a high-k dielectric material as a gate dielectric. In some embodiments, the threshold voltage of the at least one CTT may be changed by increasing or decreasing the threshold voltage.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 8, 2023
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sepideh NOURI, Subramanian IYER