Abstract: A media subsystem of a processing element includes a plurality of elements and a latency manager. The plurality of elements are capable of processing media data including a plurality of instances wherein a first element inserts a length of media data into buffer(s) from which a second element thereafter reads the length of media data for subsequent output from the media subsystem. The latency manager is capable of determining a latency requirement of the media subsystem, and then dynamically tuning the length of media data inserted into the buffer(s) based upon the latency requirement, including increasing or decreasing the length of media data inserted into the buffer(s) during one or more instances(s).

Abstract: A device (1) (and corresponding system, method and computer program product) comprises at least a first control block (2), a second control block (3), a bus (9) between the first control block (2) and the second control block (3) for transmitting information between the first control block (2) and the second control block (3), an electro-acoustic converter (5) adapted to the first control block (2) for generating an audible signal on the basis of an audio frame, video presentation means (3.8, 4) for presenting video information on the basis of video frames, and a synchronizing parameter (3.12) for synchronizing the presentation of video information to the presentation of audio information. The first control block (2) is adapted to transmit a request message to the second control block (3) for requesting an audio frame to be transmitted from the second control block (3) to the first control block (2).

Abstract: The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register (51, 52) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements (53-57) multiply the binary input signal by N+1 different tap coefficients by combining output bits of the shift register (51, 52). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.

Abstract: The invention relates to a direct-type FIR filter, a method for calculating a scalar product in a FIR filter, and a method for designing a direct-type FIR filter. Successive words of a digital input signal are delayed in a delay line having delays (50A-50D) of the duration of one word, and the scalar product between the variously delayed words derived from the delay line and the corresponding constant coefficients is calculated. In accordance with the invention, calculation of the scalar product comprises a) combining the bits of words at the input (X0) and outputs (X1-X4) of the delay line bit by bit in a network of bit-serial subtractor and/or adder elements (51-56) wherein at least one of the bit-serial elements is involved in the multiplication operation of at least two different coefficients, and b) multiplying (49A-K) the multiplication results from the network by powers of two, and summing together (45-48) the results to yield the scalar product.

Abstract: The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages (22, 23, 25, 27) and a decimation stage. The decimation filter structure of the invention comprises additional branches (28, 29, 30, 31) for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter.