Abstract: A method is provided for determining whether transmission signals are present in received signals, the method comprising: receiving a first signal via a first radio resource; receiving a second signal via a second radio resource; determining whether a first transmission signal is present in the received first signal based on the received second signal; and determining whether a second transmission signal is present in the received second signal based on the received first signal.

Abstract: A method includes generating a plurality of noise-averaged channel estimates using noisy channel estimates. At least some of the noise-averaged channel estimates are generated using different averaging lengths. The method also includes selecting one of the averaging lengths based on the plurality of noise-averaged channel estimates. The step of selecting one of the averaging lengths may include subtracting the noise-averaged channel estimates from the noisy channel estimates to produce a plurality of noise-averaged differences and determining powers of the noise-averaged differences. The step of selecting one of the averaging lengths may also include determining total error powers associated with the different averaging lengths using the powers of the noise-averaged differences and selecting the averaging length corresponding to a lowest total error power.

Abstract: Training sequence interference in an equalizer-based receiver in a time-division duplex (TDD) communication system can be avoided without using interference cancellation, by providing to the equalizer both the desired data portion of the received signal, and a portion of the training sequence that is adjacent the desired data portion and has a length commensurate with the delay spread associated with the training sequence interference. The portion of the equalizer output that corresponds to the adjacent training sequence portion can be discarded while retaining the desired equalized data.

Abstract: A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.

Abstract: An efficient architecture for a rake combiner is disclosed, for constructively combining the desired multi-path signals from a Code-Division Multiple-Access (CDMA) based system, such as a Third-Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode Wideband CDMA (W-CDMA) system, or an IS-95 CDMA system. The described rake combiner employs a single M-stage tap-delay line, an N+1 input adder, an arrangement of index offsets, pass gates, comparators and an M-stage counter to perform the combination, where M represents the delay spread in terms of symbol duration and N represents the number of rake fingers to be combined. The rake combiner architecture facilitates lowered resource requirements through use of a single tap-delay line in contrast to a conventional rake combiner which uses a series of M-stage tap-delay lines and an N input adder to perform the combination.

Abstract: A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.

Abstract: Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

Abstract: The range R of effective bits (those containing information) within the N bit output(s) from an inner modem is determined and employed to select the M soft bits passed to a channel decoder, thereby avoiding underflow or overflow degrading the channel decoder performance. The average and standard deviation of 1P values for a base-two logarithm of the N bit output are used to determine the range R of effective bits, with the N bits shifted and clipped based on the computed value of R so that the M most significant bits from that range R are passed to the channel decoder.

Abstract: Training sequence interference in an equalizer-based receiver in a time-division duplex (TDD) communication system can be avoided without using interference cancellation, by providing to the equalizer both the desired data portion of the received signal, and a portion of the training sequence that is adjacent the desired data portion and has a length commensurate with the delay spread associated with the training sequence interference. The portion of the equalizer output that corresponds to the adjacent training sequence portion can be discarded while retaining the desired equalized data.

Abstract: A method and system for estimating a frequency offset between a receiver and a transmitter, including the steps of, or means for: (a) receiving a first signal from said transmitter and demodulating the first signal; (b) performing a frequency shift on said first signal by a predetermined frequency factor to generate a second signal; (c) filtering each of said first and second signals; (d) determining the power of each of the filtered first and second signals; (e) determining an upper corner frequency value of the first signal using the power of the filtered first and second signals; (f) determining a lower corner frequency of the first signal using the determined power of the filtered first and second signals; and (g) determining a frequency offset value based on said upper corner frequency value and said lower corner frequency value.

Abstract: An efficient architecture for a rake combiner is disclosed, for constructively combining the desired multi-path signals from a Code-Division Multiple-Access (CDMA) based system, such as a Third-Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode Wideband CDMA (W-CDMA) system, or an IS-95 CDMA system. The described rake combiner employs a single M-stage tap-delay line, an N+1 input adder, an arrangement of index offsets, pass gates, comparators and an M-stage counter to perform the combination, where M represents the delay spread in terms of symbol duration and N represents the number of rake fingers to be combined. The rake combiner architecture facilitates lowered resource requirements through use of a single tap-delay line in contrast to a conventional rake combiner which uses a series of M-stage tap-delay lines and an N input adder to perform the combination.