Abstract: A system for a floor covering that includes covering panels (10A, 10B) made of a hard material, having relatively little thickness (e), with upper and lower surfaces (1a, 2a; 1b, 2b), perimetral edges (3a, 3b) and recesses (4a, 4b), and attachment parts (20) made of a relatively flexible material and having projecting members (21a, 21b) and spacing members (22a, 22b). In practice, the projecting members (21a, 21b) of the attachment parts are introduced in the recesses (4a, 4b) of the covering panels (10A, 10B) assuring the link between covering panels (10A, 10B), and the spacing members (22a, 22b) of the attachment parts (20) remain between the facing edges (3a, 3b) of the covering panels (10A, 10B) filling a gap (G) between them in the form of a joint.

Abstract: A system for a floor covering that includes covering panels (10A, 10B) made of a hard material, having relatively little thickness (e), with upper and lower surfaces (1a, 2a; 1b, 2b), perimetral edges (3a, 3b) and recesses (4a, 4b), and attachment parts (20) made of a relatively flexible material and having projecting members (21a, 21b) and spacing members (22a, 22b). In practice, the projecting members (21a, 21b) of the attachment parts are introduced in the recesses (4a, 4b) of the covering panels (10A, 10B) assuring the link between covering panels (10A, 10B), and the spacing members (22a, 22b) of the attachment parts (20) remain between the facing edges (3a, 3b) of the covering panels (10A, 10B) filling a gap (G) between them in the form of a joint.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

Abstract: According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.