Patents by Inventor Serafino Bueti
Serafino Bueti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8347019Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.Type: GrantFiled: May 16, 2008Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth Joseph Goodnow, Todd Edwin Leonard, Gregory John Mann, Jason Michael Norman, Clarence Rosser Ogilvie, Peter Anthony Sandon, Charles S. Woodruff
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Patent number: 8291357Abstract: Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors.Type: GrantFiled: October 9, 2007Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Todd E. Leonard, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
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Patent number: 8234104Abstract: A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.Type: GrantFiled: April 16, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: John Joseph Bergkvist, Jr., Serafino Bueti, Francis A. Kampf, Douglas Thomas Massey
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Patent number: 8132136Abstract: Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.Type: GrantFiled: November 8, 2007Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
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Patent number: 8016482Abstract: Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.Type: GrantFiled: July 20, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R. Bonaccio, Serafino Bueti, Hayden C. Cranford, Jr., Joseph A. Iandanza, Todd E. Leonard, Hemen R. Shah, Pradeep Thiagarajan, Sebastian T. Ventrone
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Patent number: 7941772Abstract: Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.Type: GrantFiled: August 6, 2007Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
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Patent number: 7865789Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.Type: GrantFiled: June 28, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Serafino Bueti, Adam Courchesne, Kenneth J. Goodnow, Gregory J. Mann, Jason M. Norman, Stanley B. Stanski, Scott T. Vento
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Patent number: 7823017Abstract: Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.Type: GrantFiled: March 19, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Charles S. Woodruff
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Patent number: 7823107Abstract: An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.Type: GrantFiled: October 19, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah, Sebastian T. Ventrone
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Patent number: 7716007Abstract: Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.Type: GrantFiled: June 27, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R. Bonaccio, Serafino Bueti, Hayden C. Cranford, Jr., Joseph A. Iadanza, Todd E. Leonard, Hemen R. Shah, Pradeep Thiagarajan, Sebastian T. Ventrone
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Patent number: 7643591Abstract: A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.Type: GrantFiled: July 26, 2006Date of Patent: January 5, 2010Assignee: International Business Machines CorproationInventors: Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah, Sebastian T. Ventrone
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Publication number: 20090265154Abstract: A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Inventors: John Joseph Bergkvist, JR., Serafino Bueti, Francis A. Kampf, Douglas Thomas Massey
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Patent number: 7594140Abstract: The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.Type: GrantFiled: August 2, 2006Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Charles S. Woodruff
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Publication number: 20090132747Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.Type: ApplicationFiled: May 16, 2008Publication date: May 21, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Jason M. Norman, Clarence R. Ogilvie, Peter A. Sandon, Charles S. Woodruff
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Publication number: 20090132732Abstract: A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.Type: ApplicationFiled: November 19, 2007Publication date: May 21, 2009Applicant: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Jason M. Norman, Clarence R. Ogilvie, Peter A. Sandon, Charles S. Woodruff
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Publication number: 20090106724Abstract: An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.Type: ApplicationFiled: October 19, 2007Publication date: April 23, 2009Inventors: Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah, Sebastian T. Ventrone
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Patent number: 7519941Abstract: Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.Type: GrantFiled: April 13, 2006Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Serafino Bueti, Kenneth J. Goodnow, Gregory J. Mann, Jason M. Norman
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Publication number: 20090094566Abstract: Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors.Type: ApplicationFiled: April 18, 2008Publication date: April 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Todd E. Leonard, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
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Publication number: 20090091351Abstract: Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Inventors: Serafino Bueti, Adams J. Courchesne, Kenneth J. Goodnow, Todd E. Leonard, Peter A. Sandon, Peter A. Twombly, Charles S. Woodruff
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Patent number: 7511548Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.Type: GrantFiled: December 14, 2006Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Serafino Bueti, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone