Patents by Inventor Serena Leung

Serena Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10120800
    Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 6, 2018
    Assignee: Oracle International Corporation
    Inventors: Ramaswamy Sivaramakrishnan, Serena Leung, David Smentek
  • Patent number: 9892039
    Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 13, 2018
    Assignee: Oracle International Corporation
    Inventors: Mark Luttrell, David Smentek, Ramaswamy Sivaramakrishnan, Serena Leung
  • Patent number: 9734071
    Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Oracle International Corporation
    Inventors: Serena Leung, Ramaswamy Sivaramakrishnan, Joann Lam, David Smentek
  • Publication number: 20160335184
    Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Serena Leung, Ramaswamy Sivaramakrishnan, Joann Lam, David Smentek
  • Publication number: 20160314069
    Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.
    Type: Application
    Filed: April 21, 2015
    Publication date: October 27, 2016
    Inventors: Mark Luttrell, David Smentek, Ramaswamy Sivaramakrishnan, Serena Leung
  • Publication number: 20160019149
    Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.
    Type: Application
    Filed: December 29, 2014
    Publication date: January 21, 2016
    Inventors: Ramaswamy Sivaramakrishnan, Serena Leung, David Smentek