Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via.

Abstract: A method for forming a semiconductor structure includes forming a layer stack. The method also includes forming a gate structure on the layer stack, and forming at least one cavity by removing the at least one second sacrificial layer of the layer stack. The method further includes depositing a first dielectric material, and filling the at least one cavity with the first dielectric material. Further, the method includes providing a dielectric free gate surface, free from the first dielectric material. Furthermore, the method includes depositing a second dielectric material on the dielectric free gate surface. The second dielectric material is different from the first dielectric material.

Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via.

Abstract: Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.

Abstract: Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.

Abstract: Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.

Abstract: The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A MOSFET comprising a fully germano-silicided gate electrode having a high work function is disclosed. This gate electrode is formed by a self-aligned reaction process between a silicidation metal and a semiconductor material comprising silicon and germanium. Preferably, the fully germano-silicided gate is formed by a reaction between nickel and SiGe. The work function of the fully germano-silicided gate electrode can be tuned.

Abstract: Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.

Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon.

Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.