Abstract: A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.

Abstract: A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.

Abstract: A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Abstract: This method comprises the following steps: a) providing a stack successively comprising: a substrate; a first electrode; a first dielectric layer, having a first electrical strength; a second metal electrode; a second dielectric layer, having a second dielectric strength that is strictly less than the first dielectric strength; a third electrode; the first dielectric layer and the second electrode having a first interface, the second dielectric layer and the second electrode having a second interface; b) etching the stack by bombardment with electrically charged species, so as to define resistive memory cells; the bombardment of step b) being adapted so that electrically charged species accumulate at the first and second interfaces of each resistive memory cell, so as to generate an electric field that is strictly less than the first electrical strength and is strictly greater than the second dielectric strength.

Abstract: A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Abstract: A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor.

Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.

Abstract: A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor.

Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.

Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.

Abstract: A dielectric alloy is composed of two dielectric materials that respectively have second-order non-linear dielectric susceptibilities with opposite signs. The composition is adjusted so that the alloy has a second-order non-linear dielectric susceptibility below a chosen threshold. A dielectric layer within an integrated circuit is made using the alloy. More specifically, an integrated capacitor is produced with a single-layer dielectric formed by said alloy.