Abstract: An overcharge protection circuit comprises a first series of first terminals a second series of second terminals, a first overvoltage protection device connected between each consecutive pair of first terminals, a current balancing device connected between each consecutive pair of second terminals, and a second overvoltage protection device connected between a first terminal and a second terminal. The second overvoltage protection device is configured to pass a current if a voltage over the second overvoltage protection device exceeds a threshold. The second overvoltage protection device may comprise a bidirectional ESD diode, while both the first overvoltage protection device and the second overvoltage protection device may comprise a unidirectional ESD diode.

Abstract: An overcharge protection circuit comprises a first series of first terminals a second series of second terminals, a first overvoltage protection device connected between each consecutive pair of first terminals, a current balancing device connected between each consecutive pair of second terminals, and a second overvoltage protection device connected between a first terminal and a second terminal. The second overvoltage protection device is configured to pass a current if a voltage over the second overvoltage protection device exceeds a threshold. The second overvoltage protection device may comprise a bidirectional ESD diode, while both the first overvoltage protection device and the second overvoltage protection device may comprise a unidirectional ESD diode.

Abstract: The method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm.

Abstract: A method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm.