Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude loop may include a variable gain amplifier adjusting the amplitude of the input signal. The amplitude loop can include a compression control block which may be configured either to adjust the gain in the variable gain amplifier or the voltage from the power supply based upon the operating level of the other, in addition to being based upon the amplitude correction signal, thus providing a way of maintaining the depth beyond the PA's compression point and allowing a control of the efficiency of the RF power amplifier.

Abstract: A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude correction signal may also be split into two or more signals with different frequency ranges and provided respectively to different types of power supplies with different efficiencies to generate the adjusted supply voltage to the power amplifier. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal to reduce phase distortion generated by the power amplifier.

Abstract: An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

Abstract: A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The RF power amplifier system may reduce the corrective action of the amplitude loop during periods of relatively rapid changes in amplitude, and thus distortion can be further reduced.

Abstract: A radio system includes a radio frequency (RF) integrated circuit (IC), a baseband digital signal processing (DSP) IC, and a serial digital interface coupling data there-between. In one embodiment of the invention, the RF IC has an input receiver to receive a serial digital transmission bit stream from a digital signal processing integrated circuit; a data recoverer coupled to the input receiver to recover digital data bits from the serial digital transmission bit stream; a low pass filter coupled to the data recoverer convert the digital data bits into an analog transmission signal; a mixer coupled to the low pass filter to up-convert the analog transmission signal from a baseband frequency to a second selectable carrier frequency as a transmit radio frequency signal; and an amplifier coupled to the mixer and an antenna, the amplifier to amplify the transmit radio frequency signal for broadcast over the antenna.

Abstract: A digital audio radio system includes a radio frequency (RF) integrated circuit (IC) and a baseband digital signal processing (DSP) IC to receive digital audio radio signals from satellites and terrestrial antennae. A serial digital interface couples data between the RF IC and the baseband DSP IC to provide a high data rate and low noise. In one embodiment, the RF IC has a single bit sigma delta modulator to convert an analog signal into a serial digital bit stream, and a low voltage differential output driver to reduce the output voltage swing of the serial digital bit stream. The DSP IC has a low voltage differential input receiver to increase the output voltage swing of the serial digital bit stream in the DSP IC, a decimator to lower the data rate of the serial digital bit stream, and a demodulator to convert the serial digital bit stream into parallel digital data samples for digital signal processing by the DSP IC.

Abstract: A radio system includes a radio frequency (RF) integrated circuit (IC) and a baseband digital signal processing (DSP) IC. A serial digital interface couples data between the RF IC and the DSP IC to provide a high data rate and low noise. In one embodiment, the RF IC has a single bit sigma delta modulator to convert an analog signal into a serial digital bit stream, and a differential output driver to drive the serial digital bit stream as a differential data signal. In one embodiment, the DSP IC has a differential input receiver to receive the differential data signal and generate the serial digital bit stream therein, a decimator to lower the data rate of the serial digital bit stream and convert it into parallel digital data samples, and a demodulator to digitally demodulate the parallel digital data samples into data words for digital signal processing.

Abstract: A wireless radio for wireless networking communication systems includes a radio frequency (RF) transceiver integrated circuit (IC) and a baseband digital signal processing (DSP) IC. A bidirectional serial digital interface couples data between the RF transceiver IC and the DSP IC to provide a high data rate and low noise. The bidirectional serial digital interface includes a first serial data connection and a second serial data connection. In one embodiment, the RF transceiver IC has a single bit sigma delta A/D modulator to convert an analog signal into a first serial digital bit stream for communication over the first serial data connection. In one embodiment, the DSP IC has a single bit sigma delta digital modulator to generate a second serial digital bit stream for communication over the second serial data connection.

Abstract: A transceiver (10) includes a transmitter (16) that receives a digital data stream from a digital signal processor (18) to delay lines (20, 30). The delay lines (20, 30) provide an address to a ROM look-up table (40). Another input of the look-up table (40) receives a signal that selects protocols such as TDMA, CDMA, and GSM. A multi-accumulator fractional-N synthesizer (48) receives phase derivative coefficients and a DAC (46) receives amplitude modulation coefficients from the look-up table (40) based on the selected protocol. The analog output signals from the DAC (46) and the synthesizer (48) are received by a variable gain amplifier (54) that generates an RF amplitude and frequency modulated output signal for transmission from the transmitter (16).

Abstract: A transceiver (10) includes a transmitter (16) that receives a digital data stream from a digital signal processor (18) to delay lines (20, 30). The delay lines (20,30) provide an address to a ROM look-up table (40). Another input of the look-up table (40) receives a signal that selects protocols such as TDMA, CDMA, and GSM. A multi-accumulator fractional-N synthesizer (48) receives phase derivative coefficients and a DAC (46) receives amplitude modulation coefficients from the look-up table (40) based on the selected protocol. The analog output signals from the DAC (46) and the synthesizer (48) are received by a variable gain amplifier (54) that generates an RF amplitude and frequency modulated output signal for transmission from the transmitter (16). The look-up table (40) stores phase derivative coefficients and amplitude modulation coefficients that correct for non-linearity in the variable gain amplifier (54).

Abstract: Phase shift amplifier formed by a differential pair of input transistors each collector of which transistors is connected to a respective phase shift resistor and to a phase shift capacitor, whereas the other ends of each phase shift resistor form nodes A and B respectively, while the other ends of the phase shift capacitors are connected in a cross-coupling. According to the invention, the nodes A and B are connected to the input of amplifiers of the transimpedance type at the output of which amplifiers a differential signal is available which is phase shifted relative to the differential input signal.