Abstract: A USB mass storage device includes a memory, USB interface and USB controller. A biometric circuit provides biometric authentication and a secure microcontroller is operatively connected to the biometric circuit and the USB controller and operative in accordance as a trusted platform and having a command set to access security functions and trust authentication of a user using the biometric circuit.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A USB device includes first and second communications ports and a processor operable for configuring the first communications port for connecting to a USB host and configuring the second communications port as a USB master connecting to a USB slave device. The processor can be formed as a USB device controller operatively connected to the first communications port and USB On-The-Go device controller operatively connected to a second communications port for creating a point-to-point connection to the USB slave device.

Abstract: A USB mass storage device includes a memory, USB interface and USB controller. A biometric circuit provides biometric authentication and a secure microcontroller is operatively connected to the biometric circuit and the USB controller and operative in accordance as a trusted platform and having a command set to access security functions and trust authentication of a user using the biometric circuit.

Abstract: An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.

Abstract: A secure Universal Serial Bus (USB) storage device includes a memory controller capable of storing data in and retrieving data from a memory. The secure USB storage device also includes a USB secure microcontroller capable of authorizing access to the memory through the memory controller to thereby secure the memory. The USB secure microcontroller is also capable of protecting the data stored in the memory to thereby secure contents of the memory. The USB secure microcontroller could include an SPI interface and/or a GPIO interface emulating one or more of an SPI interface and an MMC interface to the memory controller. The memory controller could include an SPI interface and/or an MMC interface to the USB secure microcontroller. The secure USB storage device may be enumerated by a USB host controller under one or more device classes.

Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.

Abstract: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

Abstract: A USB device includes first and second communications ports and a processor operable for configuring the first communications port for connecting to a USB host and configuring the second communications port as a USB master connecting to a USB slave device. The processor can be formed as a USB device controller operatively connected to the first communications port and USB On-The-Go device controller operatively connected to a second communications port for creating a point-to-point connection to the USB slave device.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.

Abstract: A universal serial bus (USB) smart card can be automatically reset from a mute mode. A processor on the smart card writes its status to a status register. A USB device controller polls the status register to determine the status of the processor. If the status from the status register indicates that the processor has entered the mute mode, the USB device controller initiates generation of a reset signal to reset the processor out of the mute mode.

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.

Abstract: A detection circuit that does not vary with the supply voltage is formed by measuring the voltage generated at the terminals of a diode (1) which is reverse biased and is supplied by a constant current generator (2). Furthermore, the generator (2) is improved by a current consumption limitation circuit (5). This circuit is particularly designed to be implanted in CMOS technology on the same substrate as a memory circuit or a microprocessor circuit.

Abstract: A circuit for the detection of a fuse with oxide vertical fusing has another fuse that is of the same type but cannot be blown and, in parallel with each of the fuses, a voltage reference circuit. The output of each of the voltage reference circuits is an input of a differential comparator. This differential comparator is preferably provided with a voltage reference circuit that is independent of the supply voltage Vcc.

Abstract: Some integrated circuits need to be protected against malfunctioning due to the variations in the supply voltage Vcc. A detector of fast variations of the supply voltage is placed in the integrated circuit to interrupt or modify all or a part of the working of the general integrated circuit in the event of the occurrence of fast variation in Vcc. The detector includes a capacitor, a current limiter, a charging circuit, and a detection transistor. The current limiter is a transistor mounted as a diode. The charging circuit uses the supply voltage to charge the capacitor through the current limiter. The relatively stable voltage of the capacitor is applied to the gate of the detection transistor, which has a threshold voltage Vtp. The source of the detection transistor is connected to the voltage supply Vcc. If Vcc varies suddenly, the detector is made conductive. The assembly uses the difference between the threshold voltage Vtn of the current limiter and the threshold voltage Vtp of the detection transistor.

Abstract: In a semi-conducting integrated circuit, there is made a light detection circuit, the output signal of which can be used to counter manipulations by dishonest persons who undertake a decapsulation or a removal from the card when the integrated circuit is inserted in a bank type card, or even a depassivation of the upper protective layer of this integrated circuit, in order to reveal the secret functioning of the circuit or to modify its characteristics. The detector comprises a current generator delivering a current of limited intensity which flows into a reversed biased electronic junction. When the junction is subjected to light, the reverse current that can be allowed into the junction increases. Since the current generator is not capable of putting through stronger current, the voltage at the terminals of the junction drops. This drop in voltage is used as information that reveals the illumination.