Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Abstract: A high performance, highly reflective ohmic contact, in the visible spectrum (400 nm–750 nm), has the following multi-layer metal profile. A uniform and thin ohmic contact material is deposited and optionally alloyed to the semiconductor surface. A thick reflector layer selected from a group that includes Al, Cu, Au, Rh, Pd, Ag and any multi-layer combinations is deposited over the ohmic contact material.

Abstract: Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.

Abstract: A device includes a submount, and a semiconductor light emitting device mounted on first and second conductive regions on a first side of the submount in a flip chip architecture configuration. The submount has third and fourth conductive regions on a second side of the submount. The third and fourth conductive regions may be used to solder the submount to structure such as a board, without the use of wire bonds. The first and third conductive regions are electrically connected by a first conductive layer and the second and fourth conductive regions are electrically connected by a second conductive layer. The first and second conductive layers may be disposed on the outside of the submount or within the submount.

Abstract: One embodiment of a process that forms low resistivity III-V nitride (e.g., GaN) p-type layers removes all sources of hydrogen (typically NH3) in the epitaxial growth chamber during the post growth cool-down process. By eliminating sources of hydrogen during the cool-down process, any additional passivation of the acceptor impurities (e.g., Mg) by hydrogen atoms during cool-down is avoided. After the cool-down process, the wafer is annealed at a relatively low temperature (e.g., below 625° C.) to remove nearly all of the hydrogen from the Mg-doped layers. The anneal can take place at a low temperature since the diffusivity of H in the p-type GaN layers is much higher than in i-type GaN layers. If the p-type layers are used in an LED, since the low temperature anneal does not degrade the GaN layers' crystallinity, the intensity of the LED's emitted light is not decreased by the anneal process.

Abstract: A light emitting device includes a heterojunction having a p-type layer and an n-type layer. The n-electrode is electrically connected to the n-type layer while the p-electrode is electrically connected to the p-type layer. The p and n-electrodes are positioned to form a region having uniform light intensity.

Abstract: N-type doping in III-V-nitride semiconductor compounds, i.e. GaN-based compounds such as GaN, AlGaN, AlInN, InGaN, or AlGaInN, can be optimized to improve N-contact electrical resistance, carrier injection, forward voltage, and recombination characteristics without inducing cracking of the device layers. The N-type layer is constructed of sub-layers such that an N-type sub-layer is provided for each desired characteristic or property. The thickness of each sub-layer is carefully selected to avoid material cracking: the higher the required doping, the smaller the corresponding thickness. In illustration, the buffer layer of a light emitting device (LED) has three sub-layers. The first sub-layer is lightly doped to avoid cracking and is grown to the desired thickness for good material quality. The second sub-layer is heavily doped to provide good N-contact and electrical resistivity characteristics and is kept correspondingly as thin as necessary to avoid material cracking.