Abstract: Apparatus and methods for displaying types of information content based on the configuration of a media device are provided. The apparatus has a plurality of display panels flexibly coupled by one or more connectors. The display panels are flexibly coupled by the one or more connectors such that the display panels are capable of being arranged in a plurality of arrangements relative to one another. Each of the arrangements is indicative of a configuration of the device media. Each of the plurality of display panels has at least one viewing surface and is configured to display on the viewing surface a type of information content. The type of information content is indicative the configuration of the media device.

Abstract: A single chip light processing system includes an on-chip light modulator on the chip and an on-chip processor on the chip. In some examples, at least a portion of the on-chip processor is formed on a different physical layer of the chip with respect to the on-chip light modulator. In some examples, an area of the on-chip processor overlaps with an area of the on-chip light modulation structure.

Abstract: A projection engine having a first kernel for modulating light of a first polarization, and a second kernel for modulating light of a second polarization, and a polarization combiner for merging light from the kernels into a dual polarization modulated output beam.

Abstract: A projection engine having a first kernel for modulating light of a first polarization, and a second kernel for modulating light of a second polarization, and a polarization combiner for merging light from the kernels into a dual polarization modulated output beam.

Abstract: An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

Abstract: A special type of random access memory referred to as video random access memory (VRAM) is used through to provide multiple access to the memory in a timely manner. The VRAM is characterized by a random access port which enables random accessing to the memory array and a serial port comprising a shift register for outputting a large group of bits of data, such as pixels representative of a scan line of a video image, which are rapidly output by the memory. In the present invention, the VRAM is utilized in a different manner to provide more efficient use of memory without degradation in system performance. The VRAM provides for communications between processors as well as the memory utilized by the coprocessor for storage of code and data. Communications between processors is performed through the serial port; therefore, data is communicated via blocks of data transfers minimizing the frequency of access to the memory array.