Abstract: This automatic equalizer comprises an automatic gain control circuit (2, 4) tending to keep the peak amplitude of the equalized signal constant, together with a variable equalization network (1) provided with a control input enabling the slope of its gain transfer characteristic to be modified without altering the value of its gain at the half Baud frequency, and a servo-control system for controlling the shaping of the frequency spectrum by controlling said variable equalization network, said servo-control system including a circuit (6) for detecting the mean phase error of zero crossings in the skirts of pulses appearing in the received and equalized digital transmission signal compared with the middles of Baud intervals.

Abstract: Frame synchronization devices utilize a frame alignment word decoder connected to the outputs of a shift register which receives on its input the received data bit stream. It is clocked by a clock signal generated from a selection of periods of the data bit stream timing signal reproducing a periodic pattern. This pattern is formed by relative bit locations within the duration of a frame certain at least of which are distributed according to the distribution of the bits of an alignment word in a frame and which form groups of the same size regularly distributed over the duration of a frame. This clock signal is generated in the device by a divider which divides by 20 or by 21 which imposes on it a periodic phase skip by the value of one period of the data bit stream timing for as long as the alignment word is not recognized by the decoder.

Abstract: A timing recovery circuit for synchronous data transmission using a signal which, in the baseband, is formed by a succession of two-level signal elements, without overlap, and of duration T, able to take one of the four forms defined by the functions: ##EQU1## comprises a transition selection circuit. This circuit selects transitions in the received signal, in the baseband, separated from those which immediately precede them by a time-delay situated in an arbitrary range. This range brackets a symbol duration of between 3/4 and 5/4 times, exclusive, the duration of a signal element. A timebase which is synchronized on the transitions selected by the selection circuit delivers the signal element recovered timing.

Abstract: In a QPSK system using one cycle of a squared-off sinusoid per Baud period to represent the data dibits, the following are disclosed:(1) a direct detection circuit using samples taken only during the second and third quarters of the Baud period;(2) timing recovery by recognition of the opposite polarity of any QPSK signal compared to a half-Baud-delayed version of itself; and(3) an encoding scheme wherein only one of the two dibits is differentially encoded.