Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.

Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).

Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.

Abstract: The invention relates to methods and apparatus suitable for executing a service or application at a client peer or client side, having a client specific device or client specific platform, with a reconfigurable architecture, said service or application being provided from a service peer or a service side. In a first aspect of the invention, the method comprises transmitting to the client peer from the server peer an abstract bytecode. The abstract bytecode is generated at the service peer by performing a compilation of an application. The abstract bytecode includes hardware bytecode and software bytecode. At the client peer, the abstract bytecode is transformed into native bytecode for the client specific device.

Abstract: A method for designing an electronic system having at least one digital part. The method includes representing a behavioral description of the system as a first set of objects with a first set of relations therebetween. Furthermore, the method includes refining said behavioral description into an implementable description of said system, said implementable description being represented as a second set of objects with a second set of relations therebetween. Also, the method includes retaining at least one of said second objects for reuse in the design of a second electronic system.

Abstract: The interprocess communication protocol system provides a generic communication system for communication between specified processes in a complex digital system. In accordance with the interprocess communication protocol, a group of pre-defined communication signals are defined, to which all communications between the processes conform. Interface hardware is disclosed to provide communication between processes. In addition, the communication protocol can be designed into the process as and integral portion of the processes.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).

Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: The present invention relates to a receiver at the head-end or a centralizing unit side in a communications system or network for signals in the upstream direction which is the direction from user to head-end or a centralizing unit that is linked to a number of users, the number being equal to or larger than one.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: A receiver is disclosed at the head-end or a centralizing unit side in a communications system or network for signals in the upstream direction which is the direction from user to head-end or a centralizing unit that is linked to a number of users, the number being equal to or larger than one. The receiver is suited for the reception of burst mode signals. The receiver performs a channel estimation on a per-burst basis in real time or essentially immediate. The channel estimation is necessary to do successful data detection of modulated data. The receiver of the invention performs the channel estimation and data detection in one compact all-digital mechanism that has no tuning parts. The reception method works in an aspect according to the principle of a matched filter receiver, but stores no local copy of the required matched waveform. Rather, a copy of the matched waveform is included in the preamble of the signals.

Abstract: The invention relates to methods and apparatus suitable for executing a service or application at a client peer or client side, having a client specific device or client specific platform, with a reconfigurable architecture, said service or application being provided from a service peer or a service side. In a first aspect of the invention, the method comprises transmitting to the client peer from the server peer an abstract bytecode. The abstract bytecode is generated at the service peer by performing a compilation of an application. The abstract bytecode includes hardware bytecode and software bytecode. At the client peer, the abstract bytecode is transformed into native bytecode for the client specific device.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: The interprocess communication protocol system provides a generic communication system for communication between specified processes in a complex digital system. In accordance with the interprocess communication protocol, a group of pre-defined communication signals are defined, to which all communications between the processes conform. Interface hardware is disclosed to provide communication between processes. In addition, the communication protocol can be designed into the process as and integral portion of the processes.