Patents by Inventor Sergei G. Rusakov

Sergei G. Rusakov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for distortion analysis in nonlinear circuits
    Patent number: 7007253
    Abstract: A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: February 28, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kiran K. Gullapalli, Mark M. Gourary, Sergei G. Rusakov, Sergei L. Ulyanov, Mikhail M. Zharov
  • Method and apparatus for distortion analysis in nonlinear circuits
    Publication number: 20040083437
    Abstract: A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.
    Type: Application
    Filed: September 8, 2003
    Publication date: April 29, 2004
    Inventors: Kiran K. Gullapalli, Mark M. Gourary, Sergei G. Rusakov, Sergei L. Ulyanov, Mikhail M. Zharov