Abstract: A computational apparatus for implementing a neural network model having multiple neurons that evaluate an activation function, the apparatus including a memory and circuitry. The memory is configured to hold values of a difference-function, each value being a respective difference between the activation function and a predefined baseline function. The circuitry is configured to evaluate the neural network model, including, for at least one of the neurons: evaluate the baseline function at the argument, retrieve from the memory one or more values of the difference-function responsively to the argument, and evaluate the activation function at the argument based on the baseline function at the argument and on the one or more values of the difference-function.

Abstract: A processor includes an internal memory and processing circuitry. The internal memory is configured to store a definition of a multi-dimensional array stored in an external memory, and indices that specify elements of the multi-dimensional array in terms of multi-dimensional coordinates of the elements within the array. The processing circuitry is configured to execute instructions in accordance with an Instruction Set Architecture (ISA) defined for the processor. At least some of the instructions in the ISA access the multi-dimensional array by operating on the multi-dimensional coordinates specified in the indices.

Abstract: A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.

Abstract: A vector processor includes a coefficient memory and a processor. The processor has an Instruction Set Architecture (ISA), which includes an instruction that approximates a mathematical function by a polynomial. The processor is configured to approximate the mathematical function over an argument, by reading one or more coefficients of the polynomial from the coefficient memory and evaluating the polynomial at the argument using the coefficients.

Abstract: Computational apparatus includes a memory, which contains first and second input matrices of input data values, having at least three dimensions including respective heights and widths in a predefined sampling space and a common depth in a feature dimension, orthogonal to the sampling space. An array of processing elements each perform a multiplication of respective first and second input operands and to accumulate products of the multiplication to generate a respective output value. Data access logic extracts first and second pluralities of vectors of the input data values extending in the feature dimension from the first and second input matrices, respectively, and distributes the input data values from the extracted vectors in sequence to the processing elements so as to cause the processing elements to compute a convolution of first and second two-dimensional matrices composed respectively of the first and second pluralities of vectors.

Abstract: An embodiment of the present invention is a technique to process an input/output (I/O) transaction. An emulated device driver in a guest partition interacts with a virtual machine (VM) manager in processing an input/output (I/O) transaction on behalf of an application via an operating system (OS). The I/O transaction is between the application and a device. A device emulator in a service partition communicatively coupled to the emulated device driver interacts with the VM manager in processing the I/O transaction on behalf of a device specific driver via the OS. The device specific driver interfaces to the device.

Abstract: A method for preventing loopback of data packets sent between entities residing on a single host. In one embodiment, an auxiliary address shared among entities residing on the host indicates that a data packet is to be routed to an entity residing on the host. In another embodiment, a source address and a target address in a data packet header are switched while being routed to a target entity residing on the host.

Abstract: Methods, apparatuses, articles, and systems for receiving a request for an allocation of one or more ephemeral ports from a pool of ephemeral ports associated with a physical device, for a virtual machine of the physical device, are described herein. In various embodiments, an ephemeral port manager of the physical device is adapted to allocate up to the one or more ephemeral ports requested from the pool of ephemeral ports, if up to the one or more ephemeral ports are available for allocation from the pool of ephemeral ports. In some embodiments, the ephemeral port manager is further adapted to mark the allocated one or more ephemeral ports as unavailable to meet an ephemeral port allocation request of another virtual machine of the physical device.

Abstract: A method for preventing loopback of data packets sent between entities residing on a single host. In one embodiment, an auxiliary address shared among entities residing on the host indicates that a data packet is to be routed to an entity residing on the host. In another embodiment, a source address and a target address in a data packet header are switched while being routed to a target entity residing on the host.

Abstract: Methods, apparatuses, articles, and systems for receiving a request for an allocation of one or more ephemeral ports from a pool of ephemeral ports associated with a physical device, for a virtual machine of the physical device, are described herein. In various embodiments, an ephemeral port manager of the physical device is adapted to allocate up to the one or more ephemeral ports requested from the pool of ephemeral ports, if up to the one or more ephemeral ports are available for allocation from the pool of ephemeral ports. In some embodiments, the ephemeral port manager is further adapted to mark the allocated one or more ephemeral ports as unavailable to meet an ephemeral port allocation request of another virtual machine of the physical device.

Abstract: An embodiment of the present invention is a technique to process an input/output (I/O) transaction. An emulated device driver in a guest partition interacts with a virtual machine (VM) manager in processing an input/output (I/O) transaction on behalf of an application via an operating system (OS). The I/O transaction is between the application and a device. A device emulator in a service partition communicatively coupled to the emulated device driver interacts with the VM manager in processing the I/O transaction on behalf of a device specific driver via the OS. The device specific driver interfaces to the device.