Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Systems and techniques involving optical coatings for semiconductor devices. An implementation includes a substantially isotropic, heterogeneous anti-reflective coating having a substantially equal thickness normal to any portion of a substrate independent of the orientation of the portion.

Abstract: An optically tuned SLAM (Sacrificial Light-Absorbing Material) may be used in a via-first dual damascene patterning process to facilitate removal of the SLAM. The monomers used to produce the optically tuned SLAM may be modified to place an optically sensitive structure in the backbone of the SLAM polymer. The wafer may be exposed to a wavelength to which the SLAM is tuned prior to etching and/or ashing steps to degrade the optically tuned SLAM and facilitate removal.

Abstract: By providing a thermal protocol that involves two steps prior to any isolation steps in a metal oxide semiconductor process, induced stress may be reduced between the bulk silicon and overlying areas, such as epitaxial layers. As a result, the dislocations in the overlying area may be reduced.

Abstract: A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjacent the front surface of a silicon wafer. A low energy silicon implant is also performed to create a plurality of gettering sites closely adjacent the front surface. Subsequently, an epitaxial silicon layer is grown on the front surface.

Abstract: In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the bulk semiconductive material within a desired active area by ion implanting at least one impurity into the bulk semiconductive material. After forming the proximity gettering region, thickness of the bulk semiconductive material is increased in a blanket manner at least within the desired active area. In one implementation, a method of processing a monocrystalline silicon substrate includes forming a proximity gettering region within monocrystalline silicon of a monocrystalline silicon substrate. After forming the proximity gettering region, epitaxial monocrystalline silicon is formed on the substrate monocrystalline silicon to blanketly increase its thickness at least over the proximity gettering region.