Patents by Inventor Sergei V. Gronin

Sergei V. Gronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230005743
    Abstract: The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.
    Type: Application
    Filed: September 1, 2022
    Publication date: January 5, 2023
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Patent number: 11488822
    Abstract: The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 1, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher, Michael James Manfra
  • Patent number: 11476118
    Abstract: A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 18, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Raymond L. Kallaher, Sergei V. Gronin
  • Publication number: 20220311216
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 29, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. GRONIN, Geoffrey Charles GARDNER, Raymond Leonard KALLAHER
  • Patent number: 11417728
    Abstract: A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than 2 ? 0 ? W m * K . The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than 2 ? 0 ? W m * K , the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 16, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond L. Kallaher, Sergei V. Gronin, Geoffrey C. Gardner
  • Patent number: 11393682
    Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 19, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher
  • Patent number: 11362487
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. Gronin, Geoffrey Charles Gardner, Raymond Leonard Kallaher
  • Publication number: 20210376572
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. GRONIN, Geoffrey Charles GARDNER, Raymond Leonard KALLAHER
  • Publication number: 20210375624
    Abstract: The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Publication number: 20210375623
    Abstract: The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 ?. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Publication number: 20210280417
    Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER
  • Publication number: 20210280763
    Abstract: A semiconductor-superconductor hybrid structure includes a semiconductor layer and a superconductor heterostructure on the semiconductor layer. The superconductor heterostructure includes a first superconductor layer on the semiconductor layer and a second superconductor layer on the first superconductor layer. The first superconductor layer comprises a first superconducting material and the second superconductor layer comprises a second superconducting material that is different from the first superconducting material. By providing the superconductor heterostructure as multiple layers of different superconducting materials, the superconducting and physical properties of the superconductor heterostructure can be improved compared to conventional superconducting homostructures, thereby increasing the performance of the semiconductor-superconductor hybrid structure.
    Type: Application
    Filed: December 23, 2019
    Publication date: September 9, 2021
    Inventors: Geoffrey C. GARDNER, Raymond L. KALLAHER, Sergei V. GRONIN, Michael James MANFRA
  • Publication number: 20210265463
    Abstract: A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than 2 ? 0 ? W m * K . The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than 2 ? 0 ? W m * K , the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Raymond L. KALLAHER, Sergei V. GRONIN, Geoffrey C. GARDNER
  • Publication number: 20210265161
    Abstract: A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Geoffrey C. GARDNER, Raymond L. KALLAHER, Sergei V. GRONIN
  • Publication number: 20210210599
    Abstract: A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Inventors: Geoffrey C. GARDNER, Sergei V. GRONIN, Raymond L. KALLAHER, Michael James MANFRA
  • Patent number: 11031243
    Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher