Patents by Inventor Sergei Victorovich SOMOV

Sergei Victorovich SOMOV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronizer with controlled metastability characteristics
    Patent number: 10868526
    Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 15, 2020
    Assignee: NXP USA, INC.
    Inventors: Mikhail Yurievich Semenov, Victor Mikhailovich Mikhailov, Sergei Victorovich Somov, Denis Borisovich Malashevich, Viacheslav Sergeyevich Kalashnikov
  • SYNCHRONIZER WITH CONTROLLED METASTABILITY CHARACTERISTICS
    Publication number: 20200195238
    Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.
    Type: Application
    Filed: July 1, 2019
    Publication date: June 18, 2020
    Inventors: Mikhail Yurievich SEMENOV, Victor Mikhailovich MIKHAILOV, Sergei Victorovich SOMOV, Denis Borisovich MALASHEVICH, Viacheslav Sergeyevich KALASHNIKOV