Abstract: A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. The method includes providing an electrical signal between the two terminals, where the electrical signal alters an electrical characteristic of a layer remote from one of the terminals. In one embodiment, the layer remote from the terminal is a chalcogenide material and the electrical characteristic is resistance. In another embodiment, an electrical characteristic of the layer in contact with the terminal is also altered. The alteration of an electrical characteristic may be caused by a transformation of a chalcogenide material from one structural state to another structural state.

Abstract: A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys may also experience faster programming and may have set and reset programming speeds that are substantially similar.

Abstract: A method of making an electrically programmable memory element, comprising: providing a first dielectric layer; forming a conductive material over the first dielectric layer; forming a second dielectric layer over the conductive material; and forming a programmable resistance material in electrical contact with a peripheral surface of the conductive material.

Abstract: Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb where a bit unintentionally changes phase.

Abstract: A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the cylindrical solid phase portion results in a more gradual transition of resistance versus programming current, enabling multilevel memories to be formed.

Abstract: A semiconductor chalcogenide containing memory device may be formed with a dielectric in close juxtaposition to a chalcogenide alloy. Because the dielectric includes material interface regions, the thermal conductivity of the dielectric is reduced. As one result, heat transfer may be reduced, reducing the programming current required to program the chalcogenide alloy.

Abstract: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated.

Abstract: An electrical device includes a composite switching material. The composite switching material includes an electrically switchable component and a non-switchable component. In one embodiment, the composite switching material includes a heterogeneous mixture of at least one chalcogenide material and at least one dielectric material. The composite switching material is disposed between two electrodes and the switchable component is transformable from a resistive state to a conductive state upon application of a voltage between the two electrodes, without changing phase.

Abstract: A method of testing a programmable resistance memory element. The method includes applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed to program the memory element from its set state to its reset state.

Abstract: A memory device includes a phase-change material and a first electrode in electrical communication with the phase-change material. Also included is a second electrode in electrical communication with the phase-change material and a dielectric layer. The dielectric layer is disposed between the first electrode and the second electrode. The dielectric layer has an opening therethrough. The phase-change material is disposed on both sides of the dielectric layer and within the opening. Electrical communication within the device is by means of virtual contacts.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A phase-change memory element comprising a phase-change memory material, a first electrical contact and a second electrical contact. At least one of the electrical contacts having a sidewall electrically coupled to the memory material.

Abstract: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.

Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area. Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode.

Abstract: A multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. In one embodiment, the pore region includes two or more chalcogenide materials which differ in chemical composition. In another embodiment, the pore region includes one or more chalcogenide materials and a layer of Sb. The devices offer the advantages of minimal conditioning requirements, fast set speeds, high reset resistances and low set resistances.

Abstract: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated.

Abstract: A chalcogenide material and chalcogenide memory device exhibiting fast operation (short set pulse times) over an extended range of reset state resistances. Electrical devices containing the instant chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio. The instant devices thus provide for high resistance contrast and improved readability of memory states while preserving fast operational speeds for the device. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. In one embodiment, the atomic concentration of Ge is between 11% and 22%, the atomic concentration of Sb is between 22% and 65%, and the atomic concentration of Te is between 28% and 55%.

Abstract: A programmable resistance memory element comprising an adhesion layer between the programmable resistance material and at least one of the electrodes. Preferably, the adhesion layer is a titanium rich titanium nitride composition.

Abstract: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.