Patents by Inventor Sergey A. Voronin

Sergey A. Voronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811273
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 20, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10237916
    Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20190080926
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10204832
    Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
  • Patent number: 10083820
    Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
  • Publication number: 20180138018
    Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Inventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
  • Publication number: 20180082903
    Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 22, 2018
    Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20170094719
    Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Patent number: 9530626
    Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jason Marion, Sonam Sherpa, Sergey A. Voronin, Alok Ranjan, Yoshio Ishikawa, Takashi Enomoto
  • Publication number: 20160027620
    Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 28, 2016
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jason MARION, Sonam SHERPA, Sergey A. VORONIN, Alok RANJAN, Yoshio ISHIKAWA, Takashi ENOMOTO
  • Patent number: 9155183
    Abstract: The present invention provides a surface wave plasma source including an electromagnetic (EM) wave launcher comprising a slot antenna having a plurality of antenna slots configured to couple the EM energy from a first region above the slot antenna to a second region below the slot antenna, and a power coupling system is coupled to the EM wave launcher. A dielectric window is positioned in the second region and has a lower surface including the plasma surface. A slotted gate plate is arranged parallel with the slot antenna and is configured to be movable relative to the slot antenna between variable opacity positions including a first opaque position to prevent the EM energy from passing through the first arrangements of antenna slots, and a first transparent position to allow a full intensity of the EM energy to pass through the first arrangement of antenna slots.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 6, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Patent number: 9101042
    Abstract: A surface wave plasma source (SWPS) is disclosed, having an electromagnetic (EM) wave launcher including a slot antenna configured to couple EM energy in a desired EM wave mode to a plasma by generating a surface wave on a plasma surface of the SWPS adjacent the plasma. The SWPS also includes a dielectric window positioned below the slot antenna, having a lower surface and the plasma surface. The SWPS further includes an attenuation assembly disposed between the slot antenna and the plasma surface. The attenuation assembly includes a first fluid channel substantially aligned with a first arrangement of slots in the slot antenna, and is configured to receive a first flow of a first fluid at a first fluid temperature. The SWPS finally includes a power coupling system coupled to the EM wave launcher and configured to provide EM energy to the EM wave launcher for forming the plasma.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 4, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20140028190
    Abstract: The present invention provides a surface wave plasma source including an electromagnetic (EM) wave launcher comprising a slot antenna having a plurality of antenna slots configured to couple the EM energy from a first region above the slot antenna to a second region below the slot antenna, and a power coupling system is coupled to the EM wave launcher. A dielectric window is positioned in the second region and has a lower surface including the plasma surface. A slotted gate plate is arranged parallel with the slot antenna and is configured to be movable relative to the slot antenna between variable opacity positions including a first opaque position to prevent the EM energy from passing through the first arrangements of antenna slots, and a first transparent position to allow a full intensity of the EM energy to pass through the first arrangement of antenna slots.
    Type: Application
    Filed: January 25, 2013
    Publication date: January 30, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20140028184
    Abstract: A surface wave plasma source (SWPS) is disclosed, having an electromagnetic (EM) wave launcher including a slot antenna configured to couple EM energy in a desired EM wave mode to a plasma by generating a surface wave on a plasma surface of the SWPS adjacent the plasma. The SWPS also includes a dielectric window positioned below the slot antenna, having a lower surface and the plasma surface. The SWPS further includes an attenuation assembly disposed between the slot antenna and the plasma surface. The attenuation assembly includes a first fluid channel substantially aligned with a first arrangement of slots in the slot antenna, and is configured to receive a first flow of a first fluid at a first fluid temperature. The SWPS finally includes a power coupling system coupled to the EM wave launcher and configured to provide EM energy to the EM wave launcher for forming the plasma.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 30, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sergey A. Voronin, Alok Ranjan