Patents by Inventor Sergey A. Voronin

Sergey A. Voronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10237916
    Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20190080926
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10204832
    Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20180323045
    Abstract: Manufacturing methods are disclosed to reduce surface particle impurities after a plasma process (e.g., etch, deposition, etc.) by repelling particles trapped within particle wells to reduce surface particle impurities on microelectronic workpieces after termination of the plasma process. Rather than turn off pressure and source power at the termination of the plasma process, the disclosed embodiments first enter a sequence to adjust process parameters to repel particles in a particle well in order to reduce or eliminate the particle well prior to terminating the plasma process. During this particle repel sequence, certain disclosed embodiments adjust parameters to maintain an electrostatic field above the surface of the wafer utilizing low plasma density and ion energy conditions that help to repel particles from the microelectronic workpiece. The disclosed methods allow for the particle well to be exhausted well prior to the collapse of electrostatic forces when the plasma process is terminated.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 8, 2018
    Inventors: Jason Marion, Yusuke Yoshida, Brendan Bathrick, Sergey Voronin, Alok Ranjan
  • Patent number: 10115591
    Abstract: Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Shyam Sridhar, Li Wang, Andrew Nolan, Hiroto Ohtake, Sergey Voronin, Alok Ranjan
  • Patent number: 10083820
    Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
  • Patent number: 10063062
    Abstract: Detecting presence or absence of plasma is accomplished from probe signals. In one embodiment, a low-power modulated signal is applied to an electrostatic chuck from a bias power generator. A corresponding system then monitors peak-to-peak voltage (Vpp) signal responses or radio frequency current responses. The probe signal can be generated to have insufficient power to either ignite or sustain plasma discharge (or cause component damage). Thus, low-duty and/or low current pulsing signals to be used. Presence or absence of the bulk plasma will then result in different Vpp or radio frequency current values.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 28, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Alok Ranjan
  • Publication number: 20180197730
    Abstract: Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.
    Type: Application
    Filed: February 23, 2017
    Publication date: July 12, 2018
    Inventors: Shyam Sridhar, Li Wang, Andrew Nolan, Hiroto Ohtake, Sergey Voronin, Alok Ranjan
  • Publication number: 20180144946
    Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 24, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sergey Voronin, Jason Marion, Yusuke Yoshida, Alok Ranjan, Takashi Enomoto, Yoshio Ishikawa
  • Publication number: 20180138018
    Abstract: Described herein is a technology related to a method for utilizing a dual-frequency surface wave plasma sources to provide stable ionizations on a plasma processing system. Particularly, the dual-frequency surface wave plasma sources may include a primary surface wave power plasma source and a secondary power plasma source, which is provided on each recess of a plurality of recesses. The secondary power plasma source, for example, may provide the stable ionization on the plasma processing system.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Inventors: Sergey A. Voronin, Jason Marion, Alok Ranjan
  • Patent number: 9966312
    Abstract: Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 8, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Alok Ranjan
  • Publication number: 20180082903
    Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 22, 2018
    Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20180019102
    Abstract: Embodiments of systems and methods for RF power distribution in a multi-zone electrode array are described. A system may include a plasma source configured to generate a plasma field. Also, the system may include an RF power source coupled to the plasma source and configured to supply RF power to the plasma source. The system may also include a source controller coupled to the RF power source and configured to control modulation of the RF power supplied to the plasma source to enhance uniformity of a plasma field generated by the plasma source.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 18, 2018
    Inventors: Sergey Voronin, Alok Ranjan
  • Publication number: 20180005805
    Abstract: Provided are methods and systems for operation instability detection in a surface wave plasma source. In an embodiment a system for plasma processing may include a surface wave plasma source configured to generate a plasma field. The system may also include an optical sensor configured to generate information characteristic of optical energy collected in a region proximate to the surface wave plasma source. Additionally, the system may include a sensor logic unit configured to detect a region of instability proximate to the surface wave plasma source in response to the information generated by the optical sensor.
    Type: Application
    Filed: January 26, 2017
    Publication date: January 4, 2018
    Inventors: Sergey Voronin, Jason Marion, Alok Ranjan
  • Patent number: 9779952
    Abstract: Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 3, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Sergey Voronin
  • Publication number: 20170094719
    Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20170062225
    Abstract: Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 2, 2017
    Inventors: Sergey Voronin, Alok Ranjan
  • Patent number: 9530626
    Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jason Marion, Sonam Sherpa, Sergey A. Voronin, Alok Ranjan, Yoshio Ishikawa, Takashi Enomoto
  • Publication number: 20160372933
    Abstract: Detecting presence or absence of plasma is accomplished from probe signals. In one embodiment, a low-power modulated signal is applied to an electrostatic chuck from a bias power generator. A corresponding system then monitors peak-to-peak voltage (Vpp) signal responses or radio frequency current responses. The probe signal can be generated to have insufficient power to either ignite or sustain plasma discharge (or cause component damage). Thus, low-duty and/or low current pulsing signals to be used. Presence or absence of the bulk plasma will then result in different Vpp or radio frequency current values.
    Type: Application
    Filed: November 18, 2015
    Publication date: December 22, 2016
    Inventors: Sergey Voronin, Alok Ranjan
  • Publication number: 20160372306
    Abstract: Techniques herein include a method for generating uniform plasma within an inductively-coupled plasma reactor. Techniques herein include providing a termination capacitor that is dynamically adjustable to adjust a termination capacitor value to provide a uniform E-field distribution in the reactor via a time-averaged uniformity. During a given plasma processing operation, a termination capacitor can be continuously changed to create various rotational cycles so that a given substrate received uniform treatment.
    Type: Application
    Filed: November 18, 2015
    Publication date: December 22, 2016
    Inventors: Sergey Voronin, Alok Ranjan