Abstract: Various apparatuses, methods and systems for boosting an amplifier slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a pair of inputs connected to a pair of differential input devices in an amplifier, a current source, a first current path connected to the current source, a second current path connected to the current source and to the pair of differential input devices, a switch in the first current path, and a voltage difference signal connected between the pair of inputs and the switch. The voltage difference signal represents the voltage difference between the pair of inputs. The conductance of the switch is inversely proportional to the voltage difference signal.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J2) and second (J4) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J2), and second input signal (Vin?) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J1) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.

Abstract: A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.

Abstract: An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.

Abstract: Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of the first transistor being coupled to receive a first signal, and a first one of the first and second electrodes of the second transistor being coupled to receive a second signal.

Abstract: A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase.

Abstract: A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase.

Abstract: An amplifier (10) includes a first stage (4) including differentially coupled first (Q1) and second (Q2) input transistors and a controlled active load circuit (6). A second stage (8) includes differentially coupled third (Q5) and fourth (Q6) input transistors and a load circuit (Q7,8). A first output (2A) of the first stage (4) is coupled to a first input of the second stage (8), a second output (2B) of the first stage (4) being coupled to a second input of the second stage (8). A common mode feedback amplifier (12) has an input coupled to receive a common mode signal (3) from the second stage (8) for producing an amplified common mode signal (9) on a control input of the controlled active load circuit (6) to provide fast settling of an output (Vout) of the second stage without substantially increasing amplifier noise.

Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through the same pair of matched input resistors which receive a differential input signal that may have both a positive and negative common mode range. An offset adjustment amplifier (17) receives a differential error signal representative of the difference between offset voltages of the first and second operational amplifiers and generates offset adjustment signals that are applied to input stages of the first and second operational amplifiers to adjust their respective offset voltages so as to equalize them.

Abstract: A differential to single-ended signal transfer circuit that allows increased gain and improved AC performance while reducing power supply voltage requirements. The transfer circuit includes a first operational transconductance amplifier (OTA), a second operational amplifier (OPA), first and second controlled current sources, a third current source, and first and second bipolar junction transistors. The inverting and non-inverting inputs of the transfer circuit are provided at the inverting input and the non-inverting input, respectively, of the OTA, which is coupled to the first and second controlled current sources to form a current mirror with tracking feedback. The output voltage of the transfer circuit is provided at the emitter of the first transistor, the base of which is connected to the non-inverting input INp. The first transistor is coupled to the third current source in an emitter follower configuration to provide both current gain and impedance matching.

Abstract: A high output current wideband output stage/buffer amplifier that has reduced quiescent current requirements. The output stage/buffer amplifier includes a diamond follower circuit having a pair of complementary output load-driving bipolar junction transistors (BJTs), a pair of pre-driver BJTs, and a plurality of current boost BJTs. As the base current of one of the driver transistors starts to increase in response to an increasing load current, the current through a corresponding pre-driver transistor decreases, thereby increasing the collector current of a corresponding boost transistor. The increased collector current of the boost transistor is fed back to a current mirror, causing a concomitant increase in the base current of the driver transistor.

Abstract: A bipolar rail-to-rail class-AB output stage that provides improved AC performance in low voltage applications. The bipolar output stage includes an input buffer stage, first and second complementary common emitter stages, and first and second control circuits biased and configured to assure class-AB operation of the first and second common emitter stages, respectively. The input of the bipolar output stage is applied to the input buffer stage, and the output of the bipolar output stage is provided by the second common emitter stage. The combination of the first common emitter stage and the first AB-control circuit operates as a current booster stage for the second common emitter stage, thereby obviating the need for a large power supply.

Abstract: A bipolar rail-to-rail class-AB output stage that provides improved AC performance in low voltage applications. The bipolar output stage includes an input buffer stage, first and second complementary common emitter stages, and first and second control circuits biased and configured to assure class-AB operation of the first and second common emitter stages, respectively. The input of the bipolar output stage is applied to the input buffer stage, and the output of the bipolar output stage is provided by the second common emitter stage. The combination of the first common emitter stage and the first AB-control circuit operates as a current booster stage for the second common emitter stage, thereby obviating the need for a large power supply.

Abstract: A differential to single-ended signal transfer circuit that allows increased gain and improved AC performance while reducing power supply voltage requirements. The transfer circuit includes a first operational transconductance amplifier (OTA), a second operational amplifier (OPA), first and second controlled current sources, a third current source, and first and second bipolar junction transistors. The inverting and non-inverting inputs of the transfer circuit are provided at the inverting input and the non-inverting input, respectively, of the OTA, which is coupled to the first and second controlled current sources to form a current mirror with tracking feedback. The output voltage of the transfer circuit is provided at the emitter of the first transistor, the base of which is connected to the non-inverting input INp. The first transistor is coupled to the third current source in an emitter follower configuration to provide both current gain and impedance matching.

Abstract: A high output current wideband output stage/buffer amplifier that has reduced quiescent current requirements. The output stage/buffer amplifier includes a diamond follower circuit having a pair of complementary output load-driving bipolar junction transistors (BJTs), a pair of pre-driver BJTs, and a plurality of current boost BJTs. As the base current of one of the driver transistors starts to increase in response to an increasing load current, the current through a corresponding pre-driver transistor decreases, thereby increasing the collector current of a corresponding boost transistor. The increased collector current of the boost transistor is fed back to a current mirror, causing a concomitant increase in the base current of the driver transistor.

Abstract: A class-AB MOS output stage that provides higher gain and significantly lower distortion. The class-AB MOS output stage includes a PMOS output transistor and an NMOS output transistor coupled between positive and negative supply voltages such that the MOS output transistors operate in a common source mode, a first biased class-AB control circuit coupled between the output transistor gates, a first current source coupled between the gate of the PMOS output transistor and the positive supply, a second biased class-AB control circuit, and a second current source coupled between the second control circuit and the positive supply. The second class-AB control circuit is coupled between the second current source and a non-inverting input of the output stage. The gate of the NMOS output transistor is employed as the inverting input of the output stage, which further includes two differential amplifiers for controlling the first and second current sources.

Abstract: A class-AB MOS output stage that provides higher gain and significantly lower distortion. The class-AB MOS output stage includes a PMOS output transistor and an NMOS output transistor coupled between positive and negative supply voltages such that the MOS output transistors operate in a common source mode, a first biased class-AB control circuit coupled between the output transistor gates, a first current source coupled between the gate of the PMOS output transistor and the positive supply, a second biased class-AB control circuit, and a second current source coupled between the second control circuit and the positive supply. The second class-AB control circuit is coupled between the second current source and a non-inverting input of the output stage. The gate of the NMOS output transistor is employed as the inverting input of the output stage, which further includes two differential amplifiers for controlling the first and second current sources.