Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.

Abstract: A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.

Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Abstract: A molded semiconductor package includes a semiconductor die embedded in a mold compound, and a plurality of metal leads embedded in the mold compound and electrically connected to the semiconductor die. A first plurality of features is formed in an exterior surface of the mold compound. The first plurality of features disrupts a planarity of the exterior surface of the mold compound and is arranged along a direction which is transverse to a lengthwise extension of the plurality of metal leads. Corresponding methods of manufacturing such a molded semiconductor package are also described.

Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Abstract: A package (120), wherein the package (120) has at least one electronic chip (124), an encapsulation body (138) that encapsulates the electronic chip(s) (124), and a plurality of terminal pins (122) to connect the electronic chip(s) (124), wherein each of the said terminal pins (122) has an encapsulated section (126), which is encapsulated at least partially by the encapsulation body (138) and has an exposed section (128) that protrudes from the encapsulation body (138), and wherein at least a portion of the exposed sections (128) laterally extends from the encapsulation body (138) up to a reversal point (130) and laterally extends back from the reversal point (130) to the encapsulation body (138), so that a free end (132) of the exposed sections (128) is laterally aligned with or to a corresponding side wall (134) of the encapsulation body (138) or is spaced from the corresponding side wall (134) of the encapsulation body (138) laterally outwardly.

Abstract: A package (120), wherein the package (120) has at least one electronic chip (124), an encapsulation body (138) that encapsulates the electronic chip(s) (124), and a plurality of terminal pins (122) to connect the electronic chip(s) (124), wherein each of the said terminal pins (122) has an encapsulated section (126), which is encapsulated at least partially by the encapsulation body (138) and has an exposed section (128) that protrudes from the encapsulation body (138), and wherein at least a portion of the exposed sections (128) laterally extends from the encapsulation body (138) up to a reversal point (130) and laterally extends back from the reversal point (130) to the encapsulation body (138), so that a free end (132) of the exposed sections (128) is laterally aligned with or to a corresponding side wall (134) of the encapsulation body (138) or is spaced from the corresponding side wall (134) of the encapsulation body (138) laterally outwardly.