Patents by Inventor Sergey Anatolievich Gorobets

Sergey Anatolievich Gorobets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220206710
    Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 30, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Alexander Bazarsky, Tien-Chien Kuo, Eran Sharon, Jack Frayer, Sergey Anatolievich Gorobets
  • Publication number: 20220139466
    Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 5, 2022
    Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Liam PARKER, Yuval SHOHET, Michelle MARTIN
  • Publication number: 20220108745
    Abstract: The present disclosure generally relates to improved foggy-fine programming. The data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
  • Publication number: 20220107751
    Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells formed on a memory die, each non-volatile memory cell configured to hold a plurality of bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data.
    Type: Application
    Filed: February 10, 2021
    Publication date: April 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Jack Frayer
  • Patent number: 11294598
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for zone formation. Each erase block comprises a plurality of wordlines. A zone comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The zone further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the zone dedicated to storing user data minus the space dedicated to metadata.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alan D. Bennett, Daniel L. Helmick, Liam Parker, Sergey Anatolievich Gorobets, Peter Grayson
  • Patent number: 11288201
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 29, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Karin Inbar, Einat Lev, Roi Kirshenbaum, Ofer Sharon, Uri Peltz, Sergey Anatolievich Gorobets, Alan David Bennett, Thomas Hugh Shippey
  • Publication number: 20220075524
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich GOROBETS, Daniel L. HELMICK, Peter GRAYSON
  • Patent number: 11226761
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die comprises a plurality of erase blocks. Each erase block comprises a plurality of wordlines. One or more wordlines are grouped together in bins. Each bin is associated with a susceptibility weight, a read count weight, a timer count weight, and a running total weight. A weight counter table is stored in the controller, and tracks the various weights associated with each bin. When a sum of the weights of each bin reaches or exceeds a predetermined value, the controller closes the erase block to avoid an unacceptable quantity of bit error accumulation. The bit error susceptibility of an erase block decreases after the erase block is at capacity or is closed.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 18, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liam Parker, Daniel L. Helmick, Alan D. Bennett, Sergey Anatolievich Gorobets
  • Patent number: 11211119
    Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: December 28, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
  • Publication number: 20210397383
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller restricts the host to a maximum number of zones that can be in the open and active state at a time. Open zones can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open zones is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a zone from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Liam PARKER, Daniel L. HELMICK, Sergey Anatolievich GOROBETS
  • Publication number: 20210391002
    Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Thomas Hugh SHIPPEY, Ryan R. JONES
  • Patent number: 11194521
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. The controller restricts the host to a maximum number of streams that can be in the open and active state at a time. Open streams can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open streams is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a stream from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 7, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Daniel L. Helmick, Liam Parker
  • Patent number: 11194494
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 7, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Daniel L. Helmick, Peter Grayson
  • Publication number: 20210374003
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Peter GRAYSON, Sergey Anatolievich GOROBETS
  • Publication number: 20210373804
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. The controller restricts the host to a maximum number of streams that can be in the open and active state at a time. Open streams can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open streams is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a stream from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich GOROBETS, Daniel L. HELMICK, Liam PARKER
  • Publication number: 20210334041
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for zone formation. Each erase block comprises a plurality of wordlines. A zone comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The zone further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the zone dedicated to storing user data minus the space dedicated to metadata.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alan D. BENNETT, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS, Peter GRAYSON
  • Publication number: 20210333997
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich GOROBETS, Daniel L. HELMICK, Peter GRAYSON
  • Publication number: 20210333996
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. A first command to write data to a first stream is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first stream. When a second command to write data to a second stream is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second stream is copied from the parking section to the RAM1. The second parity data is updated in the RAM1 with the data of the second command and copied to the parking section.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich GOROBETS, Peter GRAYSON, Daniel L. HELMICK, Liam PARKER
  • Publication number: 20210334031
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second zone is copied from the parking section to the RAM1. The second parity data is then updated in the RAM1 with the data of the second command and copied to the parking section.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Peter GRAYSON, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS
  • Publication number: 20210334032
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die comprises a plurality of erase blocks. Each erase block comprises a plurality of wordlines. One or more wordlines are grouped together in bins. Each bin is associated with a susceptibility weight, a read count weight, a timer count weight, and a running total weight. A weight counter table is stored in the controller, and tracks the various weights associated with each bin. When a sum of the weights of each bin reaches or exceeds a predetermined value, the controller closes the erase block to avoid an unacceptable quantity of bit error accumulation. The bit error susceptibility of an erase block decreases after the erase block is at capacity or is closed.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Liam PARKER, Daniel L. HELMICK, Alan D. BENNETT, Sergey Anatolievich GOROBETS