Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamically resizing logical storage blocks. A controller for a non-volatile storage device includes a block component that determines a total number of available erase blocks of the non-volatile storage device. A controller for a non-volatile storage device includes a size module that determines numbers of erase blocks from available erase blocks to include in each of a plurality of logical blocks as a function of a total number of available erase blocks such that the numbers of erase blocks for each of the logical blocks deviates from each other by less than a predetermined deviation limit. A controller for a non-volatile storage device includes a map module that generates logical blocks for the non-volatile storage device by assigning determined numbers of erase blocks to each of the logical blocks.

Abstract: A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: A die assignment scheme assigns data in the order it is received, to multiple memory dies. Any busy dies are skipped until they become ready again so that the system does not wait for busy dies to become ready. Immediately sequential writes to the same die are prohibited so that reading speed is not impacted.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.

Abstract: The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Abstract: A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.

Abstract: A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: A die assignment scheme assigns data in the order it is received, to multiple memory dies. Any busy dies are skipped until they become ready again so that the system does not wait for busy dies to become ready. Immediately sequential writes to the same die are prohibited so that reading speed is not impacted.

Abstract: The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Abstract: A memory unit has a busy control system that includes a busy control register that may be written by a controller. The contents of the busy control register determine whether a signal is sent from the memory unit to the controller and, if so, which of a plurality of signals is sent. A signal may automatically be sent from a selected memory unit and masked from an unselected unit.

Abstract: A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

Abstract: Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.

Abstract: A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.

Abstract: A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.

Abstract: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.

Abstract: In a memory system with a file storage system, a scheme for allocating memory locations for a write operation is to write the files substantially contiguously in a memory block one after another rather than to start a new file in a new block. In this way, they are more efficiently packed into the blocks by being written contiguously one after another. In a preferred embodiment, an incrementing write pointer points to the write location in memory for the next data for a file, which is independent of the offset address of the data within the file. When a current write block becomes filled with file data, an erased block is allocated, and the write pointer is moved to this block. Similarly a relocation pointer is used for data relocation during garbage collection or data compaction operations.