Abstract: A memory tester for testing memory devices. The tester comprises a test header, an algorithmic pattern generator (APG) and a fault logic device. In the memory tester according to the invention successive data processing algorithms with minimum feedbacks are used. The APG generates test instructions wherein each instruction has fields controlling respective functional parts of the tester. The control signals are stored together with data signals in an instruction memory that provides high speed test pattern generation. For different memory types, the width of instruction memory varies.

Abstract: A handling assembly for handling integrated circuits and trays for receiving these integrated circuits, the handling assembly comprising at least one integrated circuit manipulator having a holder pivoted on a fixed axis of rotation; the holder having a plurality of grippers arranged substantially in the plane passing through said axis of rotation, the holder being adapted to rotate said plurality of grippers at least to a first and second angular positions, a tray transporter adapted to move a tray into an operational position in which at least one of the integrated circuits in the tray is engageable by at least one of the grippers rotated to the first angular position, and an integrated circuit receiving/releasing means engageable by at least one of the grippers rotated to the second angular position.